DSP EPWM模块中有描述说：给定0%和100%占空比可能会存在延迟一周期更新的问题，具体什么情况下会出现这种情况有详细的描述吗？并且官方还出了文档SPRAAI1来说明如何输出0%和100%。现在项目中把比较值直接给零或者周期值实验发现不会出现延迟一周期更新的问题，想知道具体隐患在哪里？
TMS320F28034 RM手册3.2.4.4节原文：
The waveforms in this document show the ePWMs behavior for a static compare register
value. In a running system, the active compare registers (CMPA and CMPB) are typically
updated from their respective shadow registers once every period. The user specifies when
the update will take place; either when the time-base counter reaches zero or when the timebase
counter reaches period. There are some cases when the action based on the new
value can be delayed by one period or the action based on the old value can take effect for
an extra period. Some PWM configurations avoid this situation. These include, but are not
limited to, the following: |
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