4.声明各系统时钟配置函数(system_stm32f10x.c)
//声明各系统时钟配置函数
#ifdef SYSCLK_FREQ_HSE
static void SetSysClockToHSE(void);
#elif defined SYSCLK_FREQ_16MHz
static void SetSysClockTo16(void);
#elif defined SYSCLK_FREQ_24MHz
static void SetSysClockTo24(void);
#elif defined SYSCLK_FREQ_36MHz
static void SetSysClockTo36(void);
#elif defined SYSCLK_FREQ_48MHz
static void SetSysClockTo48(void);
#elif defined SYSCLK_FREQ_56MHz
static void SetSysClockTo56(void);
#elif defined SYSCLK_FREQ_72MHz
static void SetSysClockTo72(void);
#endif
5.调用各系统时钟配置函数(system_stm32f10x.c)
//调用各系统时钟配置函数
static void SetSysClock(void)
{
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE(); //8MHz
#elif defined SYSCLK_FREQ_16MHz
SetSysClockTo16(); //16MHz
#elif defined SYSCLK_FREQ_24MHz
SetSysClockTo24(); //24MHz
#elif defined SYSCLK_FREQ_36MHz
SetSysClockTo36(); //36MHz
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48(); //48MHz
#elif defined SYSCLK_FREQ_56MHz
SetSysClockTo56(); //56MHz
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72(); //72MHz
#endif
/* If none of the define above is enabled, the HSI is used as System clock
source (default after reset) */
}
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
其中不同配置需要改的地方:
1)选择FLASH_ACR_LATENCY:
FLASH_ACR_LATENCY_0/FLASH_ACR_LATENCY_1/FLASH_ACR_LATENCY_2
FLASH_ACR_LATENCY的选择:
STM32的FLASH手册上,关于FLASH_ACR寄存器的LATENCY位的说明,上面明确写着:
0 wait state if 0MHz < SYSCLK <= 24MHz
1 wait state if 24MHz < SYSCLK <= 48MHz
2 wait state if 48MHz < SYSCLK <= 72MHz
2)配置PLL时钟: