iobuf是什么东东？看看我的编译结果~ microblaze 求助~

只看该作者 · 2012-3-16 18:20

本帖最后由 sunmax 于 2012-3-16 21:44 编辑

iobuf?我什么时候用它呢？有点懵了~~~求指点。
我的编译结果
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_rst_1_sys_rst_pin_IBUF" LOC = K17>' could not be found and so
the Locate constraint will be removed.

还有：
WARNING:NgdBuild:1345 - The constraint <TIMESPEC TS_sys_clk_pin = PERIOD
"sys_clk_pin" 50000.000000000 KHz HIGH 50.000000000 %;> is overridden by the
constraint <TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;>
[sys_pin.ucf(14)]. The overriden constraint usually comes from the input
netlist or ncf files. Please set XIL_NGDBUILD_CONSTR_OVERRIDE_ERROR to
promote this message to an error.

只看该作者 · 2012-3-16 18:41

不是很明白
猴哥来帮忙
帮顶

只看该作者 · 2012-3-16 20:01

输入输出端口的缓冲，IBUF AND OBUF

只看该作者 · 2012-3-16 20:33

3# Backkom80
我的警告能否解决一下。。。。我是将microblaze软核加入编译时遇到的问题

只看该作者 · 2012-3-16 20:40

这两个警告都是说约束在有无较的约束
第一个是说约束的腿腿的
第二个是说sys_clk这个时钟的周期约束的
检查设计中这两个是不是被优化了。

只看该作者 · 2012-3-16 21:41

本帖最后由 sunmax 于 2012-3-16 21:45 编辑

5# Backkom80
#  Spartan-3E Starter Board
Net fpga_0_RS232_DCE_RX_pin LOC=R7  |  IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_DCE_TX_pin LOC=M14  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> LOC=F9  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> LOC=E9  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> LOC=D11  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> LOC=C11  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> LOC=F11  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> LOC=E11  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> LOC=E12  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> LOC=F12  |  IOSTANDARD = LVCMOS33;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC=c9  |  IOSTANDARD = LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=K17  |  IOSTANDARD = LVCMOS33  |  PULLDOWN ;

这是我的约束文件  关于编译出来的NET "fpga_0_rst_1_sys_rst_pin_IBUF"我根本没有啊，工程中我都没添加这样的IBUF。。。。
这是 cpu类化文件：
// Instantiate the module
(* BOX_TYPE = "user_black_box" *)
cpu_led instance_name (
.fpga_0_RS232_DCE_RX_pin(fpga_0_RS232_DCE_RX_pin),
.fpga_0_RS232_DCE_TX_pin(fpga_0_RS232_DCE_TX_pin),
.fpga_0_LEDs_8Bit_GPIO_IO_O_pin(fpga_0_LEDs_8Bit_GPIO_IO_O_pin),
.fpga_0_clk_1_sys_clk_pin(fpga_0_clk_1_sys_clk_pin),
.fpga_0_rst_1_sys_rst_pin(fpga_0_rst_1_sys_rst_pin)
);
这是我的top实现：
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:30:34 03/16/2012
// Design Name:
// Module Name: system
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module system( fpga_0_RS232_DCE_RX_pin,
            fpga_0_RS232_DCE_TX_pin,
   fpga_0_LEDs_8Bit_GPIO_IO_O_pin,
   fpga_0_clk_1_sys_clk_pin,
   fpga_0_rst_1_sys_rst_pin
);

input fpga_0_RS232_DCE_RX_pin;
input fpga_0_clk_1_sys_clk_pin;
input fpga_0_rst_1_sys_rst_pin;
output [0:7] fpga_0_LEDs_8Bit_GPIO_IO_O_pin;
output fpga_0_RS232_DCE_TX_pin;
// Instantiate the module
(* BOX_TYPE = "user_black_box" *)
cpu_led instance_name (
.fpga_0_RS232_DCE_RX_pin(fpga_0_RS232_DCE_RX_pin),
.fpga_0_RS232_DCE_TX_pin(fpga_0_RS232_DCE_TX_pin),
.fpga_0_LEDs_8Bit_GPIO_IO_O_pin(fpga_0_LEDs_8Bit_GPIO_IO_O_pin),
.fpga_0_clk_1_sys_clk_pin(fpga_0_clk_1_sys_clk_pin),
.fpga_0_rst_1_sys_rst_pin(fpga_0_rst_1_sys_rst_pin)
);
endmodule

请求支援啊~~~~

只看该作者 · 2012-3-16 21:43

5# Backkom80
这是所有的警告
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_rst_1_sys_rst_pin_IBUF" LOC = K17>' could not be found and so
the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_clk_1_sys_clk_pin_IBUFG" LOC = C9>' could not be found and so
the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_RS232_DCE_TX_pin_OBUF" LOC = M14>' could not be found and so
the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_RS232_DCE_RX_pin_IBUF" LOC = R7>' could not be found and so the
Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_LEDs_8Bit_GPIO_IO_O_pin_7_OBUF" LOC = F12>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_LEDs_8Bit_GPIO_IO_O_pin_6_OBUF" LOC = E12>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_LEDs_8Bit_GPIO_IO_O_pin_5_OBUF" LOC = E11>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_LEDs_8Bit_GPIO_IO_O_pin_4_OBUF" LOC = F11>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_LEDs_8Bit_GPIO_IO_O_pin_3_OBUF" LOC = C11>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_LEDs_8Bit_GPIO_IO_O_pin_2_OBUF" LOC = D11>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_LEDs_8Bit_GPIO_IO_O_pin_1_OBUF" LOC = E9>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<NET "fpga_0_LEDs_8Bit_GPIO_IO_O_pin_0_OBUF" LOC = F9>' could not be found
and so the Locate constraint will be removed.
WARNING:NgdBuild:1345 - The constraint <TIMESPEC TS_sys_clk_pin = PERIOD
"sys_clk_pin" 50000.000000000 KHz HIGH 50.000000000 %;> is overridden by the
constraint <TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;>
[sys_pin.ucf(14)]. The overriden constraint usually comes from the input
netlist or ncf files. Please set XIL_NGDBUILD_CONSTR_OVERRIDE_ERROR to
promote this message to an error.
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_rst_1_sys_rst_pin_IBUF"
IOSTANDARD = "LVCMOS33"> is overridden on the design object
fpga_0_rst_1_sys_rst_pin by the constraint <IOSTANDARD = LVCMOS33  |>
[sys_pin.ucf(18)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_rst_1_sys_rst_pin_IBUF" LOC
= K17> is overridden on the design object fpga_0_rst_1_sys_rst_pin by the
constraint <Net fpga_0_rst_1_sys_rst_pin LOC=K17  |> [sys_pin.ucf(18)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_clk_1_sys_clk_pin_IBUFG"
IOSTANDARD = "LVCMOS33"> is overridden on the design object
fpga_0_clk_1_sys_clk_pin by the constraint <IOSTANDARD = LVCMOS33;>
[sys_pin.ucf(15)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_clk_1_sys_clk_pin_IBUFG" LOC
= C9> is overridden on the design object fpga_0_clk_1_sys_clk_pin by the
constraint <Net fpga_0_clk_1_sys_clk_pin LOC=c9  |> [sys_pin.ucf(15)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_RS232_DCE_TX_pin_OBUF"
IOSTANDARD = "LVCMOS33"> is overridden on the design object
fpga_0_RS232_DCE_TX_pin by the constraint <IOSTANDARD = LVCMOS33;>
[sys_pin.ucf(3)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_RS232_DCE_TX_pin_OBUF" LOC =
M14> is overridden on the design object fpga_0_RS232_DCE_TX_pin by the
constraint <Net fpga_0_RS232_DCE_TX_pin LOC=M14  |> [sys_pin.ucf(3)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_RS232_DCE_RX_pin_IBUF"
IOSTANDARD = "LVCMOS33"> is overridden on the design object
fpga_0_RS232_DCE_RX_pin by the constraint <IOSTANDARD = LVCMOS33;>
[sys_pin.ucf(2)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_RS232_DCE_RX_pin_IBUF" LOC =
R7> is overridden on the design object fpga_0_RS232_DCE_RX_pin by the
constraint <Net fpga_0_RS232_DCE_RX_pin LOC=R7  |> [sys_pin.ucf(2)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_7_OBUF" IOSTANDARD = "LVCMOS33"> is
overridden on the design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> by the
constraint <IOSTANDARD = LVCMOS33;> [sys_pin.ucf(12)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_7_OBUF" LOC = F12> is overridden on the
design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> by the constraint <Net
fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> LOC=F12  |> [sys_pin.ucf(12)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_6_OBUF" IOSTANDARD = "LVCMOS33"> is
overridden on the design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> by the
constraint <IOSTANDARD = LVCMOS33;> [sys_pin.ucf(11)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_6_OBUF" LOC = E12> is overridden on the
design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> by the constraint <Net
fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> LOC=E12  |> [sys_pin.ucf(11)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_5_OBUF" IOSTANDARD = "LVCMOS33"> is
overridden on the design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> by the
constraint <IOSTANDARD = LVCMOS33;> [sys_pin.ucf(10)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_5_OBUF" LOC = E11> is overridden on the
design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> by the constraint <Net
fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> LOC=E11  |> [sys_pin.ucf(10)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_4_OBUF" IOSTANDARD = "LVCMOS33"> is
overridden on the design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> by the
constraint <IOSTANDARD = LVCMOS33;> [sys_pin.ucf(9)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_4_OBUF" LOC = F11> is overridden on the
design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> by the constraint <Net
fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> LOC=F11  |> [sys_pin.ucf(9)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_3_OBUF" IOSTANDARD = "LVCMOS33"> is
overridden on the design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> by the
constraint <IOSTANDARD = LVCMOS33;> [sys_pin.ucf(8)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_3_OBUF" LOC = C11> is overridden on the
design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> by the constraint <Net
fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> LOC=C11  |> [sys_pin.ucf(8)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_2_OBUF" IOSTANDARD = "LVCMOS33"> is
overridden on the design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> by the
constraint <IOSTANDARD = LVCMOS33;> [sys_pin.ucf(7)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_2_OBUF" LOC = D11> is overridden on the
design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> by the constraint <Net
fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> LOC=D11  |> [sys_pin.ucf(7)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_1_OBUF" IOSTANDARD = "LVCMOS33"> is
overridden on the design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> by the
constraint <IOSTANDARD = LVCMOS33;> [sys_pin.ucf(6)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_1_OBUF" LOC = E9> is overridden on the design
object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> by the constraint <Net
fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> LOC=E9  |> [sys_pin.ucf(6)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_0_OBUF" IOSTANDARD = "LVCMOS33"> is
overridden on the design object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> by the
constraint <IOSTANDARD = LVCMOS33;> [sys_pin.ucf(5)].
WARNING:NgdBuild:1012 - The constraint <NET
"fpga_0_LEDs_8Bit_GPIO_IO_O_pin_0_OBUF" LOC = F9> is overridden on the design
object fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> by the constraint <Net
fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> LOC=F9  |> [sys_pin.ucf(5)].
WARNING:NgdBuild:478 - clock net instance_name/mdm_0/bscan_drck1 with clock
driver instance_name/mdm_0/mdm_0/BUFG_DRCK1 drives no clock pins
WARNING:PhysDesignRules:367 - The signal <instance_name/dlmb_LMB_ABus<31>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <instance_name/dlmb_LMB_ABus<30>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:Par:288 - The signal instance_name/dlmb_LMB_ABus<31> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal instance_name/dlmb_LMB_ABus<30> has no load.  PAR will not attempt to route this signal.
Phase  8  : 0 unrouted; WARNING:Route:455 - CLK Net:instance_name/mdm_0/Dbg_Update_1 may have excessive skew because
WARNING:Route:455 - CLK Net:fpga_0_clk_1_sys_clk_pin_IBUFG may have excessive skew because
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

只看该作者 · 2012-3-16 21:47

6# sunmax

这是生成的rtl图~~~

只看该作者 · 2012-3-17 09:52

呵呵不知是不是你的.ucf写的有问题，你这么写试试呢，感觉少了“”;

NET "rst_n" LOC = A13  | IOSTANDARD = LVCMOS33 ;
NET "clk_40m"  LOC = C13  | IOSTANDARD = LVCMOS33 ;
NET "clk_160m" LOC = B14  | IOSTANDARD = LVCMOS33 ;

腿腿那要有一个引号的，不知是不少了这个引号的原故。

时钟约束那也是，少了引号：
NET "clk_160m" TNM_NET = "clk_160m";
TIMESPEC "TS_clk_160m" = PERIOD "clk_160m" 5.883 ns HIGH 50.00% INPUT_JITTER 100ps;

试试吧，:lol

只看该作者 · 2012-3-17 16:34

本帖最后由 sunmax 于 2012-3-17 16:35 编辑

:lol问题解决了，xps生成的ucf，在ise中会自动读取，不需要你再次加入，就这样问题解决了，继续前进~~~

只看该作者 · 2012-3-17 22:25

本帖最后由 zuphen 于 2012-3-17 22:26 编辑

10# sunmax

刚才看到了你的已经结贴的帖子，看到你也在使用Microblaze软核，我也在使用，希望能和你多交流交流。
另外，你帖子里说“xps生成的ucf，在ise中会自动读取”，的确是这样。XPS在完成Microblaze软核的制作以后，会把软核的硬件定义（好像是MHS文件）和XPS的约束（UCF）联合起来，生成一个叫GNC的文件（好像名字不对，有点记不清了，呵呵），这个文件不仅包含软核的描述，也包含约束，所以在ISE中使用软核，软核的约束都不需要再写进UCF。假如你在软核中使用了DDR3，并且在XPS中对DDR3进行了约束，那么在ISE中就不需要再对DDR3的做任何的约束了。
呵呵，也许我讲的你都知道，那就直接忽略好了。我只是希望能够多交流交流，共同进步。