AT32F403A_407 内置的PLL最高可输出240 MHz时钟,时钟高于72MHz时设定略有不同,须根据输出频率设定PLLRANGE寄存器
#define RCC_CFG_PLLRANGE_GT72MHZ ((uint32_t)0x80000000
例如AT32F403A PLL设定程序范例:(HSE = 8 MHz, PLL = 240 MHz)
RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ);
开启滑顺功能:
RCC_StepModeCmd(ENABLE);
关闭滑顺功能:
RCC_StepModeCmd(DISABLE);
开/关滑顺功能函数定义:
void RCC_StepModeCmd(FunctionalState NewState)
{
assert_param(IS_FUNCTIONAL_STATE(NewState));
if(NewState == ENABLE)
{
RCC->MISC2 |= RCC_MISC2_AUTO_STEP_EN;
}
else
{
RCC->MISC2 &= ~RCC_MISC2_AUTO_STEP_EN;
}
注:PLL 等于72MHz 设定和SXX32F103 是一样
SXX32F103 PLL 设定程序范例:(HSE = 8 MHz, PLL = 72 MHz)
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
AT32F403A PLL 设定程序范例:(HSE = 8 MHz, PLL = 72 MHz)
RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT9);
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