8位PIC芯片汇编环境搭建——pic-as汇编

    #include <xc.inc>



; CONFIG1

  CONFIG  FEXTOSC = OFF         ; External Oscillator Mode Selection bits (Oscillator not enabled)

  CONFIG  RSTOSC = HFINTOSC_32MHZ; Power-up Default Value for COSC bits (HFINTOSC (32 MHz))

  CONFIG  CLKOUTEN = OFF        ; Clock Out Enable bit (CLKOUT function is disabled; I/O function on RA4)

  CONFIG  VDDAR = HI            ; VDD Range Analog Calibration Selection bit (Internal analog systems are calibrated for operation between VDD = 2.3V - 5.5V)



; CONFIG2

  CONFIG  MCLRE = EXTMCLR       ; Master Clear Enable bit (If LVP = 0, MCLR pin is MCLR; If LVP = 1, RA3 pin function is MCLR)

  CONFIG  PWRTS = PWRT_OFF      ; Power-up Timer Selection bits (PWRT is disabled)

  CONFIG  WDTE = OFF            ; WDT Operating Mode bits (WDT disabled; SEN is ignored)

  CONFIG  BOREN = ON            ; Brown-out Reset Enable bits (Brown-out Reset Enabled, SBOREN bit is ignored)

  CONFIG  BORV = LO             ; Brown-out Reset Voltage Selection bit (Brown-out Reset Voltage (VBOR) set to 1.9V)

  CONFIG  PPS1WAY = ON          ; PPSLOCKED One-Way Set Enable bit (The PPSLOCKED bit can be set once after an unlocking sequence is executed; once PPSLOCKED is set, all future changes to PPS registers are prevented)

  CONFIG  STVREN = ON           ; Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will cause a reset)



; CONFIG3



; CONFIG4

  CONFIG  BBSIZE = BB512        ; Boot Block Size Selection bits (512 words boot block size)

  CONFIG  BBEN = OFF            ; Boot Block Enable bit (Boot Block is disabled)

  CONFIG  SAFEN = OFF           ; SAF Enable bit (SAF is disabled)

  CONFIG  WRTAPP = OFF          ; Application Block Write Protection bit (Application Block is not write-protected)

  CONFIG  WRTB = OFF            ; Boot Block Write Protection bit (Boot Block is not write-protected)

  CONFIG  WRTC = OFF            ; Configuration Registers Write Protection bit (Configuration Registers are not write-protected)

  CONFIG  WRTSAF = OFF          ; Storage Area Flash (SAF) Write Protection bit (SAF is not write-protected)

  CONFIG  LVP = ON              ; Low Voltage Programming Enable bit (Low Voltage programming enabled. MCLR/Vpp pin function is MCLR. MCLRE Configuration bit is ignored.)



; CONFIG5

  CONFIG  CP = OFF              ; User Program Flash Memory Code Protection bit (User Program Flash Memory code protection is disabled)

;CONFIG WDTE=OFF // WDT Disabled; SWDTEN is ignored



;this must be linked to the reset vector

PSECT resetVec,class=CODE,reloc=1

resetVec:

    GOTO main



    

PSECT code    

main:

    ; This code example illustrates initializing the PORTA register.

; The other ports are initialized in the same manner.

BANKSEL PORTA ;

CLRF PORTA ;Clear PORTA

BANKSEL LATA ;

CLRF LATA ;Clear Data Latch

BANKSEL ANSELA ;

CLRF ANSELA ;Enable digital drivers

BANKSEL TRISA ;

MOVLW 00111000B ;Set RA[5:3] as inputs

MOVWF TRISA ;and set others as outputs

    END

-presetVec=0h,-Map=led.map