在FPGA内手动做Delay

只看该作者 · 2012-4-15 15:42

RickySu
引用功能被关闭了。
1. 确定要delay的信号是时钟信号还是数据信号。
如果是free running的时钟信号，频率在DCM操作范围之内，要记得使用DCM做Phase Shift。
2. 如果是V5，可以用ODELAY
3. 如果有一个快速的时钟，而要做一个大于一个时钟的delay，那么可以用shift register。SRL16可以将一个LUT当16个Shift register使。
4. 如果以上条件都不满足，就只好用LUT搭延时链了。
如果不要求动态改变延时长度，那么就多次使用这样的LUT：
引用
  LUT4 delay( .I0(1'b1), .I1(1'b1), .I2(1'b1), .I3(clk_in), .O(delay1) );
  defparam delay.INIT = 16'hff00;
  // synthesis attribute INIT of delay is "ff00";
引用
  LUT4_u0 : LUT4
  generic map (
   INIT => X"ff00")
  port map (
   O => delay_out, -- LUT general output
   I0 => '0', -- LUT input
   I1 => '0', -- LUT input
   I2 => '0', -- LUT input
   I3 => delay_in  -- LUT input
  );

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// Preparation for data to be sent to the memory
`timescale 1 ns/1 ps
module cq_delay(clk_in,sel_in,clk_out);

input    clk_in ;
input[4:0]  sel_in;
output    clk_out;

wire       clk_in ;
wire [4:0]  sel_in;
wire       clk_out1, clk_out2;
wire       clk_out;


wire delay1 /* synthesis syn_keep = 1 */;
wire delay2 /* synthesis syn_keep = 1 */;
wire delay3 /* synthesis syn_keep = 1 */;
wire delay4 /* synthesis syn_keep = 1 */;
wire delay5 /* synthesis syn_keep = 1 */;

LUT4 one( .I0(1'b1), .I1(sel_in[4]), .I2(delay5), .I3(clk_in), .O(clk_out));
// synthesis attribute INIT of one is "f3c0";
defparam one.INIT = 16'hf3c0;

LUT4 two( .I0(clk_in), .I1(sel_in[2]), .I2(1'b1), .I3(delay3), .O(delay4));
defparam two.INIT = 16'hee22;
// synthesis attribute INIT of two is "ee22";

LUT4 three( .I0(clk_in), .I1(sel_in[0]), .I2(delay1), .I3(1'b1), .O(delay2) );
defparam three.INIT = 16'he2e2;
// synthesis attribute INIT of three is "e2e2";

LUT4 four( .I0(1'b1), .I1(1'b1), .I2(1'b1), .I3(clk_in), .O(delay1) );
defparam four.INIT = 16'hff00;
// synthesis attribute INIT of four is "ff00";

LUT4 five( .I0(1'b1), .I1(sel_in[3]), .I2(delay4), .I3(clk_in), .O(delay5) );
defparam five.INIT = 16'hf3c0;
// synthesis attribute INIT of five is "f3c0";

LUT4 six( .I0(clk_in), .I1(sel_in[1]), .I2(delay2), .I3(1'b1), .O(delay3) );
defparam six.INIT = 16'he2e2;
// synthesis attribute INIT of six is "e2e2";
// assign #1 clk_out2 = clk_out1;
// assign    clk_out = clk_out2;