module bcd60counter(clk,switch,count);
input clk,switch;
output[7:0]count;
reg[7:0]count=8'b0;
always@(posedge clk)
begin
if(switch)
begin
count=count+8'b1;
//若低四位向高四位进位
if(count[3:0]==4'b1010)
count=count+8'b00000110;
//若到了60
if(count==8'b01100000)
count=0;
end
else
begin
//count=count-8'b1;
//若低四位向高四位借位
if(count[3:0]==4'b0000)
begin
//count[3:0]=4'b1010
count=count-8'b1;
count=count-8'b00000110;
end
else
count=count-8'b1;
if(count==8'b00000000-8'b00000111)
count=8'b01011001;
end
end
endmodule
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