帮我看看mpc862的bsp的几个文件,看有什么问题

只看该作者 · 2008-5-21 09:40

文件:860pc.h

/* dab.h - Motorola MPC860DAB board header */

#ifndef        INCdabh
#define        INCdabh

#include "drv/mem/memDev.h"
#include "drv/intrCtl/ppc860Intr.h"

#define BUS        0                                /* bus-less board */
#define CPU        PPC860                                /* CPU type */

#define N_SIO_CHANNELS                 1                /* No. serial I/O channels */

#define FREQ_40_MHZ                40000000        /* 40 Mhz        */

/*
* SPLL Multiplication Factor: use to set the MF bits of the PLPRCR register.
* PLPRCR is set by sysHwInit() in sysLib.c.
* SPLL_FREQ_REQUESTED and CRISTAL_FREQ are defined in config.h
*/
#define SPLL_MUL_FACTOR        ((SPLL_FREQ_REQUESTED / CRISTAL_FREQ) - 1)
/*
* SPLL Multiplication Factor to get a 40 MHZ running frequency
*/
#define SPLL_MUL_FACTOR_40MHZ        ((FREQ_40_MHZ / CRISTAL_FREQ) - 1)

#define SPLL_FREQ        ((SPLL_MUL_FACTOR + 1) * CRISTAL_FREQ)

#define BRGCLK_FREQ        FREQ_40_MHZ

#define TMBCLK_FREQ        CRISTAL_FREQ /4

#define DEC_CLOCK_FREQ                TMBCLK_FREQ

#define INTERNAL_MEM_MAP_ADDR                0xFF000000
#define INTERNAL_MEM_MAP_SIZE                0x00010000        /* 64 K bytes */

/* Ethernet parameters */

#ifdef  INCLUDE_CPM                                /* CPM ethernet driver */
#define INCLUDE_IF_USR
#define IF_USR_NAME     "cpm"                   /* device name */
#define IF_USR_ATTACH   cpmattach               /* driver attach routine */
                                                /* address of SCC param RAM */
#define IF_USR_ARG1     (char *) INTERNAL_MEM_MAP_ADDR + 0x3c00
                                                /* address of SCC regs */
#define IF_USR_ARG2     (int)INTERNAL_MEM_MAP_ADDR + 0x0a00
#define IF_USR_ARG3     (int) IV_SCC1           /* int number for SCC1 */
                                                /* address of transmit BDs */
#define IF_USR_ARG4     (int) INTERNAL_MEM_MAP_ADDR + 0x2000
                                                /* address of receive BDs */
#define IF_USR_ARG5     (int) INTERNAL_MEM_MAP_ADDR + 0x2100
#define IF_USR_ARG6     (int) 0x20              /* number of transmit BDs */
#define IF_USR_ARG7     (int) 0x20              /* number of receive BDs */
#define IF_USR_ARG8     (int) NONE              /* allocate mem for buffers */
#endif  /* INCLUDE_CPM */
#endif /* INCdabh */

只看该作者 · 2008-5-21 09:41

文件:config.h
/* dab/config.h - Motorola MPC860DAB board configuration header */

#ifndef        INCconfigh
#define        INCconfigh

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "1.2"
#define BSP_REV         "/4  (c) ESDL(Beijing), 2000" /* 0 for the first bsp revision */

#include "configAll.h"

#define DEFAULT_BOOT_LINE
"cpm(0,0)msrm_test:vxWorks h=192.168.1.11 e=192.168.1.200 u=vxworks pw=vxworks"

#undef EDO_DRAM

/* Cache and MMU not supported */
#define USER_I_MMU_ENABLE
#define USER_D_MMU_ENABLE
#define INCLUDE_MMU_BASIC

#undef USER_I_MMU_ENABLE
#undef USER_D_MMU_ENABLE
#undef INCLUDE_MMU_BASIC

#undef USER_I_CACHE_ENABLE
#undef USER_D_CACHE_ENABLE

/* Number of TTY definition */
#undef        NUM_TTY
#define        NUM_TTY                N_SIO_CHANNELS                /* defined in dab.h */

#undef        INCLUDE_TIMESTAMP

/* clock rates */
#define        SYS_CLK_RATE_MIN        1        /* minimum system clock rate */
#define        SYS_CLK_RATE_MAX        8000        /* maximum system clock rate */
#define        AUX_CLK_RATE_MIN        0        /* minimum auxiliary clock rate */
#define        AUX_CLK_RATE_MAX        0        /* maximum auxiliary clock rate */

/*
* Cristal Frequency - This macro defines the input oscillator frequency
* clocking the PPC860. On the DAB board, the CPU is clocked by a cristal
* running at 4 Mhz.
*/

#define CRISTAL_FREQ                4000000                        /* 4 Mhz */

/*
* SPLL_FREQ_REQUESTED - This macro defined the expected system PLL (SPLL)
* frequency divided by 2. The two supported frequencies are either 25
* or 40 MHz.
*/
#define SPLL_FREQ_REQUESTED        FREQ_40_MHZ                /* 40 Mhz */

#define BRGCLK_DIV_FACTOR  0

/* add necessary drivers */
#define INCLUDE_END              /* Enhanced Network Driver see configNet.h */
#define INCLUDE_CPM                        /* include the CPM ethernet driver */

/* remove unnecessary drivers */
#undef INCLUDE_BP
#undef INCLUDE_EX
#undef INCLUDE_ENP
#undef INCLUDE_SM_NET
#undef INCLUDE_SM_SEQ_ADD

/* Memory addresses */
#define LOCAL_MEM_LOCAL_ADRS        0x00000000        /* Base of RAM */
#define LOCAL_MEM_SIZE                0x00800000        /* 8 Mbyte memory available */

#define ROM_BASE_ADRS                0x00800000        /* base address of ROM */
#define ROM_TEXT_ADRS                ROM_BASE_ADRS + 0x100
#define ROM_SIZE                0x00400000         /* 4M ROM space */

/* RAM address for ROM boot */
#define RAM_HIGH_ADRS                (LOCAL_MEM_LOCAL_ADRS + 0x00300000)
/* RAM address for sys image */
#define RAM_LOW_ADRS                (LOCAL_MEM_LOCAL_ADRS + 0x00010000)

#define USER_RESERVED_MEM        0x00000000        /* user reserved memory size */

/*
* Default power management mode - selected via vxPowerModeSet() in
* sysHwInit().
*/

#define DEFAULT_POWER_MGT_MODE  VX_POWER_MODE_DISABLE

#include "860pc.h"                                /* include the DAB params */
#endif        /* INCconfigh */

/* The following has been added by WindCfg */
#include "configdb.h"

#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif

只看该作者 · 2008-5-21 09:42

文件:makefile

# Makefile - makefile for bsp/config/dab

CPU              = PPC860
TOOL             = gnu

TGT_DIR = $(WIND_BASE)/target

include $(TGT_DIR)/h/make/defs.bsp
include $(TGT_DIR)/h/make/make.$(CPU)$(TOOL)
include $(TGT_DIR)/h/make/defs.$(WIND_HOST_TYPE)

## Only redefine make definitions below this point, or your definitions will
## be overwritten by the makefile stubs above.

TARGET_DIR        = 860pc
VENDOR                = Motorola
BOARD                = 860pc

## The constants ROM_TEXT_ADRS, ROM_SIZE, and RAM_HIGH_ADRS are defined
## in config.h and Makefile. All definitions for these constants must be
## identical.

ROM_TEXT_ADRS    = 00800100 # ROM entry address
ROM_SIZE         = 00400000 # number of bytes of ROM space

RAM_LOW_ADRS     = 00010000 # RAM text/data address
RAM_HIGH_ADRS    = 00300000 # RAM text/data address

HEX_FLAGS        = -a $(ROM_TEXT_ADRS)

MACH_EXTRA       =

## Only redefine make definitions above this point, or the expansion of
## makefile target dependencies may be incorrect.

include $(TGT_DIR)/h/make/rules.bsp
include $(TGT_DIR)/h/make/rules.$(WIND_HOST_TYPE)

只看该作者 · 2008-5-21 09:43

/* romInit.s - Motorola 860DAB ROM initialization module */

#define        _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"

        /* internals */

        .globl        _romInit        /* start of system code */
        .globl        romInit                /* start of system code */

        /* externals */

        .extern romStart        /* system initialization routine */

        .text
        .align 2

_romInit:
romInit:
        bl        cold                /* jump to the cold boot initialization */

        bl        start                /* jump to the warm boot initialization */

        /* copyright notice appears at beginning of ROM (in TEXT segment) */

        .ascii   "Copyright 1984-1996 Wind River Systems, Inc."
        .align 2

cold:
        li        r3, BOOT_COLD        /* set cold boot as start type */

        lis        r4, HIADJ(start)                /* load r4 with the address */
        addi        r4, r4, LO(start)                /* of start */

        lis        r5, HIADJ(romInit)                /* load r5 with the address */
        addi        r5, r5, LO(romInit)                /* of romInit() */

        lis        r6, HIADJ(ROM_TEXT_ADRS)        /* load r6 with the address */
        addi        r6, r6, LO(ROM_TEXT_ADRS)        /* of ROM_TEXT_ADRS */

        sub        r4, r4, r5                        /*  */
        add        r4, r4, r6

        mtspr        LR, r4                                /* save destination address*/
                                                /* into LR register */
        blr                                        /* jump to flash mem address */

start:
        /* set the MSR register to a known state */
        xor        r4, r4, r4                /* clear register R4 */
        mtmsr         r4                        /* cleat the MSR register */
        /* DER - clear the Debug Enable Register */
        mtspr        DER, r4
        /* ICR - clear the Interrupt Cause Register */
        mtspr        ICR, r4
        /*ICTRL - initialize the Intstruction Support Control register*/
        lis        r5, HIADJ(0x00000007)
        addi        r5, r5, LO(0x00000007)
        mtspr        ICTRL, r5
        /* disable the instruction/data cache */
        lis        r4, HIADJ ( CACHE_CMD_DISABLE)                /* load disable cmd */
        addi        r4, r4, LO (CACHE_CMD_DISABLE)
        mtspr        IC_CST, r4                                /* disable I cache */
        mtspr        DC_CST, r4                                /* disable D cache */
        /* unlock the instruction/data cache */
        lis        r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)        /* load unlock cmd */
        addi        r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
        mtspr        IC_CST, r4                        /* unlock all I cache lines */
        mtspr        DC_CST, r4                        /* unlock all D cache lines */
        /* invalidate the instruction/data cache */
        lis        r4, HIADJ ( CACHE_CMD_INVALIDATE)        /* load invalidate cmd*/
        addi        r4, r4, LO (CACHE_CMD_INVALIDATE)
        mtspr        IC_CST, r4                /* invalidate all I cache lines */
        mtspr        DC_CST, r4                /* invalidate all D cache lines */
        /*
         * initialize the IMMR register before any non-core registers
         * modification.
         */

        lis        r4, HIADJ( INTERNAL_MEM_MAP_ADDR)
        addi        r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
        mtspr        IMMR, r4                /* initialize the IMMR register */

        mfspr        r4, IMMR                /* read it back, to be sure */
        rlwinm  r4, r4, 0, 0, 15        /* only high 16 bits count */

        /* SYPCR - turn off the system protection stuff */

        lis        r5, HIADJ( 0xFFFFFF08)
        addi        r5, r5, LO(0xFFFFFF08)
        stw        r5, SYPCR(0)(r4)

        /* set the SIUMCR register for important debug port, etc... stuff */

        lis        r5, HIADJ( 0x00600400)
        addi        r5, r5, LO(0x00600400)
        stw        r5, SIUMCR(0)(r4)

        /* TBSCR - initialize the Time Base Status and Control register */

        lis        r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
        addi        r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
        sth        r5, TBSCR(0)(r4)

        /* set PIT status and control init value */

        li        r5, PISCR_PS | PISCR_PITF
        sth        r5, PISCR(0)(r4)

        /* set the SPLL frequency to 40 Mhz : Mo */
        /*
        lis        r5, HIADJ( 0x00800000)
        addi        r5, r5, LO(0x00800000)
        stw        r5, SCCR(0)(r4)
        */
        lis        r5, HIADJ( (SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) |
                                                                PLPRCR_TEXPS)
        addi        r5, r5, LO((SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) |
                                                                PLPRCR_TEXPS)
        stw        r5, PLPRCR(0)(r4)

  /* Select the UPM table for SDRAM */

        lis        r6, HIADJ( UpmTable)
        addi        r6, r6, LO(UpmTable)

        lis        r7, HIADJ( UpmTableEnd)
        addi        r7, r7, LO(UpmTableEnd)
        b        upmInit

upmInit:
        /* init UPMA for memory access */

        sub        r5, r7, r6                /* compute table size */
        srawi        r5, r5, 2                /* in integer size */

        /* convert UpmTable to ROM based addressing */

        lis        r7, HIADJ(romInit)
        addi        r7, r7, LO(romInit)

        lis        r8, HIADJ(ROM_TEXT_ADRS)
        addi        r8, r8, LO(ROM_TEXT_ADRS)

        sub        r6, r6, r7                /* subtract romInit base address */
        add        r6, r6, r8                 /* add in ROM_TEXT_ADRS address */


        lis        r9, HIADJ ( 0x0 )
        addi        r9, r9, LO( 0x0 )

UpmWriteLoop:
        /* write the UPM table in the UPM */

        lwz        r10, 0(r6)                /* get data from table */
        stw        r10, MDR(0)(r4)                /* store the data to MD register */

        stw        r9, MCR(0)(r4)                /* issue command to MCR register */

        addi        r6, r6, 4                /* next entry in the table */
        addi        r9, r9, 1                /* next MAD address */
        cmpw        r9, r5                        /* done yet ? */
        blt        UpmWriteLoop
/**/
        lis        r5, HIADJ( 0xFF800E00)
        addi        r5, r5, LO(0xFF800E00)
        stw        r5, OR2(0)(r4)

        lis        r5, HIADJ( 0x00000081)
        addi        r5, r5, LO( 0x00000081)
        stw        r5, BR2(0)(r4)

        lis        r5, HIADJ( 0x4E802114 )
        addi        r5, r5, LO(0x4E802114 )
        stw        r5, MAMR(0)(r4)

        li        r5, 0x0800
        sth        r5, MPTPR(0)(r4)

        li        r5, 0x0000
        sth        r5, MSTAT(0)(r4)
/**/
        lis        r5, HIADJ( 0xffffffff)
        addi        r5, r5, LO(0xffffffff )
        stw        r5, MDR(0)(r4)

        lis        r5, HIADJ( 0x00000088)
        addi        r5, r5, LO(0x00000088 )
        stw        r5, MAR(0)(r4)

        lis        r5, HIADJ( 0x80004110)
        addi        r5, r5, LO(0x80004110 )
        stw        r5, MCR(0)(r4)

        lis        r5, HIADJ( 0x80004811)
        addi        r5, r5, LO(0x80004811 )
        stw        r5, MCR(0)(r4)

        lis        r5, HIADJ( 0x80004116)
        addi        r5, r5, LO(0x80004116 )
        stw        r5, MCR(0)(r4)

/**/
sdramInit:
        /* Map the bank 2 to the SDram area */

        lis        r5, HIADJ( 0xFF800E00 )
        addi        r5, r5, LO( 0xFF800E00 )
        stw        r5, OR2(0)(r4)

        lis        r5, HIADJ( 0x00000081 )
        addi        r5, r5, LO(0x00000081 )
        stw        r5, BR2(0)(r4)

        lis        r5, HIADJ( 0x4E802114 )
        addi        r5, r5, LO( 0x4E802114 )
        stw        r5, MAMR(0)(r4)

        /*
         * Map the bank 0 to the flash area - On the 860pc board at reset time
         * the bank 0 is already used to map the flash.
         */
        lis        r5, HIADJ(0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, BR1(0)(r4)

        lis        r5, HIADJ(0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, OR1(0)(r4)

        lis        r5, HIADJ( 0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, BR5(0)(r4)

        lis        r5, HIADJ(0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, OR5(0)(r4)

        lis        r5, HIADJ( 0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, BR3(0)(r4)

        lis        r5, HIADJ(0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, OR3(0)(r4)

        lis        r5, HIADJ( 0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, BR4(0)(r4)

        lis        r5, HIADJ(0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, OR4(0)(r4)

        lis        r5, HIADJ( 0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, BR6(0)(r4)

        lis        r5, HIADJ(0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, OR6(0)(r4)

        lis        r5, HIADJ( 0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, BR7(0)(r4)

        lis        r5, HIADJ(0x00000000)
        addi        r5, r5, LO(0x00000000)
        stw        r5, OR7(0)(r4)

        lis        r5, HIADJ( 0x00800001)
        addi        r5, r5, LO(0x00800001)
        stw        r5, BR0(0)(r4)

        lis        r5, HIADJ( 0xFFC00920 )
        addi        r5, r5, LO(0xFFC00920 )
        stw        r5, OR0(0)(r4)

        /* initialize the stack pointer */

        lis        sp, HIADJ(STACK_ADRS)
        addi        sp, sp, LO(STACK_ADRS)

        /* go to C entry point */

        addi        sp, sp, -FRAMEBASESZ                /* get frame stack */

        /*
         * calculate C entry point: routine - entry point + ROM base
         * routine        = romStart
         * entry point        = romInit        = R7
         * ROM base        = ROM_TEXT_ADRS = R8
         * C entry point: romStart - R7 + R8
         */

        lis        r6, HIADJ(romStart)
        addi        r6, r6, LO(romStart)                /* load R6 with C entry point */

        sub        r6, r6, r7                        /* routine - entry point */
        add        r6, r6, r8                         /* + ROM base */

        mtlr        r6                                /* move C entry point to LR */
        blr                                        /* jump to the C entry point */

UpmTable:
   /* single read. (offset 0 in upm RAM) */
.long   0x0f0dfc24, 0x0ffffc04, 0x00bf7c04, 0x0ffdf400
.long   0x1ffffc05, 0x0ffffc04, 0x0FFFFC04, 0x1ffffc05

   /* burst read. (offset 8 in upm RAM) */
.long   0x0f0dfc24, 0x0ffffc04, 0x00bf7c04, 0x00fffc00
.long   0x00fffc00, 0x00fffc00, 0x0ffdf400, 0x1ffdfc05
.long   0x0ffdf405, 0x0ffd7c84, 0xfffffc04, 0xfffffc04
.long   0xfffffc84, 0xfffffc05, 0x0f0d7434, 0xfffffc05

   /* single write. (offset 18 in upm RAM) */
.long   0x0f0dfc24, 0x0ffffc00, 0x00bf7404, 0x0ffffc04
.long   0x0ffdf404, 0x1ffffc05, 0xfffffc44, 0xfffffd47

   /* burst write. (offset 20 in upm RAM) */
.long   0x0f0dfc24, 0x0ffffc00, 0x00bf7400, 0x00fffc00
.long   0x00fffc00, 0x00fffc04, 0x00fffc04, 0x0ffdf404
.long   0x1ffffc05, 0xfffffc47, 0xfffffc04, 0xfffffc04
.long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04

   /* refresh. (offset 30 in upm RAM) */
.long   0x0ffd7c84, 0x0ffffc04, 0x0ffffc04, 0x0ffffc84
.long   0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04

/* exception. (offset 3c in upm RAM) */
.long   0x7ffffc07, 0xffffffff, 0xffffffff, 0xffffffff

UpmTableEnd:

只看该作者 · 2008-5-21 09:45

不使用mmu和cache,我想是不是已经禁止了?

现在的问题是进入到taskactivate后,停在里面了

2万 · 2008-5-21 09:57

呵呵，
咱们等你捐了钱了再来回复你啊....

只看该作者 · 2008-5-22 09:29

现在发现,是停在一个叫做dllInsert()函数里,是被taskActivate()调用的.

我一个同事也照着模板做了一个,同样也是停在这里.难道说,是硬件的问题?

我的板子很简单,硬件上的初始化感觉都还可以:flash,sdram 能写能读,时钟频率跟设定的一样.闪灯程序也可以跑(不论是在flash里,还是在sdram里).

其他,还有啥?

只看该作者 · 2008-5-24 01:24

你贴的这些东西只要能启动就没啥问题。。。。

有没有MMU看你usrMmuInit编了没有。。

taskActivate为什么会挂住跟你taskSpawn有关系。。。自己查吧

只看该作者 · 2008-5-31 14:34

现在改了线，没问题了。

奶奶的，郁闷了一个月

帮我看看mpc862的bsp的几个文件,看有什么问题

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这个文件关于sdram的部分应该没问题

急啊,同志们.四川地震了,最近心情也不好!

多捐点钱，心情就好了哦~

虽然钱挣得很辛苦,也还是心系灾区,钱我已经捐了.

。。。

唉，郁闷，硬件错误

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