帮我看看这个频率计程序啊，测不准啊

只看该作者 · 2012-5-3 13:38

module cymometer(seg7,scan,sysclk,clkin,clk_out,clk_div);
output clk_out;
output[7:0] seg7;
output[7:0] scan;
output clk_div;
input sysclk;
input clkin;
reg [7:0] seg7;
reg [7:0] scan;
reg [24:0] cnt;
reg [15:0]cnt1;
reg clk_cnt;
reg[3:0] cntp1,cntp2,cntp3,cntp4,cntp5,cntp6,cntp7,cntp8;
reg[3:0] cntq1,cntq2,cntq3,cntq4,cntq5,cntq6,cntq7,cntq8;
reg[3:0] dat;
reg clk_out;
reg clk_div;
/*******************************************************/
always @(posedge sysclk)
begin
if(cnt==25'b1_0111_1101_0111_1000_0100_0000)
  begin clk_cnt<=~clk_cnt;cnt<=0;end
else
  begin
cnt<=cnt+1'b1;
  end
end
/***********************************************************/
always @(posedge sysclk)
begin
if(cnt1==16'd1999)
  begin clk_div<=~clk_div;cnt1<=0;end
else
  begin
cnt1<=cnt1+1'b1;
  end
end
/**************************************************************/
always @(posedge clkin)
begin
if(clk_cnt)
  begin
if(cntp1==4'b1001)
begin cntp1<=4'b0000;cntp2<=cntp2+1'b1;
   if(cntp2==4'b1001)
   begin cntp2<=4'b0000;cntp3<=cntp3+1'b1;
   if(cntp3==4'b1001)
      begin cntp3<=4'b0000;cntp4<=cntp4+1'b1;
      if(cntp4==4'b1001)
      begin cntp4<=4'b0000;cntp5<=cntp5+1'b1;
         if(cntp5==4'b1001)
         begin cntp5<=4'b0000;cntp6<=cntp6+1'b1;
         if(cntp6==4'b1001)
            begin cntp6<=4'b0000;cntp7<=cntp7+1'b1;
            if(cntp7==4'b1001)
            begin cntp7<=4'b0000;cntp8<=cntp8+1'b1;
               if(cntp8==4'b1001)
               begin cntp8<=4'b0000;end
            end
            end
         end
      end
      end
   end
end
else begin cntp1<=cntp1+1'b1;clk_out<=~clk_out; end
  end
else
  begin
if(cntp1!='b0000|cntp2!='b0000|cntp3!='b0000|cntp4!='b0000|cntp5!='b0000|cntp6!='b0000|cntp7!='b000|cntp8!='b0000)
begin
   cntq1<=cntp1;cntq2<=cntp2;cntq3<=cntp3;
   cntq4<=cntp4;cntq5<=cntp5;cntq6<=cntp6;
   cntq7<=cntp7;cntq8<=cntp8;
   cntp1<=4'b0000;cntp2<=4'b0000;cntp3<=4'b0000;
   cntp4<=4'b0000;cntp5<=4'b0000;cntp6<=4'b0000;
   cntp7<=4'b0000;cntp8<=4'b0000;
end
  end
end
always
begin
case(cnt[15:13])
  'b000:begin scan<='b01111111;dat<=cntq1;end
  'b001:begin scan<='b10111111;dat<=cntq2;end
  'b010:begin scan<='b11011111;dat<=cntq3;end
  'b011:begin scan<='b11101111;dat<=cntq4;end
  'b100:begin scan<='b11110111;dat<=cntq5;end
  'b101:begin scan<='b11111011;dat<=cntq6;end
  'b110:begin scan<='b11111101;dat<=cntq7;end
  'b111:begin scan<='b11111110;dat<=cntq8;end
  default:begin scan<=8'bx;dat<=4'bx;end
endcase
case(dat[3:0])
  'b0000:seg7[7:0]=8'b1100_0000;
  'b0001:seg7[7:0]=8'b1111_1001;
  'b0010:seg7[7:0]=8'b1010_0100;
  'b0011:seg7[7:0]=8'b1011_0000;
  'b0100:seg7[7:0]=8'b1001_1001;
  'b0101:seg7[7:0]=8'b1001_0010;
  'b0110:seg7[7:0]=8'b1000_0010;
  'b0111:seg7[7:0]=8'b1111_1000;
  'b1000:seg7[7:0]=8'b1000_0000;
  'b1001:seg7[7:0]=8'b1001_0000;
  default seg7[7:0]='bx;
endcase
end
endmodule