HotCRC CRC16R_A001_0000_0000 FPGA模块 HotPower@163.com（菜农独创）

/*-----------------------------------------------------------------------------------------------

      HotCRC CRC16R_A001_0000_0000 FPGA模块 HotPower[url=home.php?mod=space&uid=516618]@163.com[/url] 2023-09-21 10:56:23

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module CRC16R_A001(clk, rst, data, outcrc16)

input clk, rst;

input [7:0] data;

output reg[15:0] outcrc16;

reg [15:0] crc16;



task CRC16R_A001;

inout[15:0] crc16;

input[7:0] indata;

    crc16 = crc16[15:8] ^ CRC16R_A001_Table(crc16[7:0] ^ indata);

endtask



function [15:0] CRC16R_A001_Table;

    input [7:0] data;

    CRC16R_A001_Table = CRC16R_A001_Table0(data[1:0]) ^ CRC16R_A001_Table1(data[3:2]) ^ CRC16R_A001_Table2(data[5:4]) ^ CRC16R_A001_Table3(data[7:6]);

endfunction



function [15:0] CRC16R_A001_Table0;

    input[1:0] data;

    case(data)

        2'b00: CRC16R_A001_Table0 = 16'h0000; 2'b01: CRC16R_A001_Table0 = 16'hC0C1; 2'b10: CRC16R_A001_Table0 = 16'hC181; 2'b11: CRC16R_A001_Table0 = 16'h0140;

        default: CRC16R_A001_Table0 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16R_A001_Table1;

    input[1:0] data;

    case(data)

        2'b00: CRC16R_A001_Table1 = 16'h0000; 2'b01: CRC16R_A001_Table1 = 16'hC301; 2'b10: CRC16R_A001_Table1 = 16'hC601; 2'b11: CRC16R_A001_Table1 = 16'h0500;

        default: CRC16R_A001_Table1 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16R_A001_Table2;

    input[1:0] data;

    case(data)

        2'b00: CRC16R_A001_Table2 = 16'h0000; 2'b01: CRC16R_A001_Table2 = 16'hCC01; 2'b10: CRC16R_A001_Table2 = 16'hD801; 2'b11: CRC16R_A001_Table2 = 16'h1400;

        default: CRC16R_A001_Table2 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16R_A001_Table3;

    input[1:0] data;

    case(data)

        2'b00: CRC16R_A001_Table3 = 16'h0000; 2'b01: CRC16R_A001_Table3 = 16'hF001; 2'b10: CRC16R_A001_Table3 = 16'hA001; 2'b11: CRC16R_A001_Table3 = 16'h5000;

        default: CRC16R_A001_Table3 = 16'h0000;

    endcase

endfunction





always @(posedge clk or negedge rst)

begin

    if (!rst)

    begin

        crc16 <= 16'h0000;

    end

    else

    begin

        CRC16R_A001(crc16, data);

        outcrc16 <= crc16;

        crc16 <= crc16;

    end

end

endmodule