HotCRC CRC16L_8005_0000_0000 FPGA模块 HotPower@163.com（菜农独创）

/*-----------------------------------------------------------------------------------------------

      HotCRC CRC16L_8005_0000_0000 FPGA模块 HotPower[url=home.php?mod=space&uid=516618]@163.com[/url] 2023-09-21 11:58:59

-----------------------------------------------------------------------------------------------*/

module CRC16L_8005(clk, rst, data, outcrc16)

input clk, rst;

input [7:0] data;

output reg[15:0] outcrc16;

reg [15:0] crc16;



task CRC16L_8005;

inout[15:0] crc16;

input[7:0] indata;

    crc16 = {crc16[7:0], 8'h00} ^ CRC16L_8005_Table(crc16[15:8] ^ indata);

endtask



function [15:0] CRC16L_8005_Table;

    input [7:0] data;

    CRC16L_8005_Table = CRC16L_8005_Table0(data[1:0]) ^ CRC16L_8005_Table1(data[3:2]) ^ CRC16L_8005_Table2(data[5:4]) ^ CRC16L_8005_Table3(data[7:6]);

endfunction



function [15:0] CRC16L_8005_Table0;

    input[1:0] data;

    case(data)

        2'b00: CRC16L_8005_Table0 = 16'h0000; 2'b01: CRC16L_8005_Table0 = 16'h8005; 2'b10: CRC16L_8005_Table0 = 16'h800F; 2'b11: CRC16L_8005_Table0 = 16'h000A;

        default: CRC16L_8005_Table0 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16L_8005_Table1;

    input[1:0] data;

    case(data)

        2'b00: CRC16L_8005_Table1 = 16'h0000; 2'b01: CRC16L_8005_Table1 = 16'h801B; 2'b10: CRC16L_8005_Table1 = 16'h8033; 2'b11: CRC16L_8005_Table1 = 16'h0028;

        default: CRC16L_8005_Table1 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16L_8005_Table2;

    input[1:0] data;

    case(data)

        2'b00: CRC16L_8005_Table2 = 16'h0000; 2'b01: CRC16L_8005_Table2 = 16'h8063; 2'b10: CRC16L_8005_Table2 = 16'h80C3; 2'b11: CRC16L_8005_Table2 = 16'h00A0;

        default: CRC16L_8005_Table2 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16L_8005_Table3;

    input[1:0] data;

    case(data)

        2'b00: CRC16L_8005_Table3 = 16'h0000; 2'b01: CRC16L_8005_Table3 = 16'h8183; 2'b10: CRC16L_8005_Table3 = 16'h8303; 2'b11: CRC16L_8005_Table3 = 16'h0280;

        default: CRC16L_8005_Table3 = 16'h0000;

    endcase

endfunction





always [url=home.php?mod=space&uid=72445]@[/url] (posedge clk or negedge rst)

begin

    if (!rst)

    begin

        crc16 <= 16'h0000;

    end

    else

    begin

        CRC16L_8005(crc16, data);

        outcrc16 <= crc16;

        crc16 <= crc16;

    end

end

endmodule