/*clk=9.63MHz
*counter=clk/wanted_freq/2;
*/
module test(reset,clk,led1,led2,led3);
input reset;
input clk;
output led1,led2,led3;
reg led1,led2,led3;
/*generate 1hz*/
reg clk_1hz;
reg[31:0] counter1;
always@(posedge clk or posedge reset)
begin
if(reset)
counter1=0;
else
begin
if(counter1==4800000)
counter1<=0;
else
counter1<=counter1+1;
end
end
always@(posedge clk or posedge reset)
begin
if(reset)
clk_1hz=0;
else
if(counter1==4800000)
clk_1hz=~clk_1hz;
end
/*state loop*/
parameter [1:0]
s1=2'b00,
s2=2'b01,
s3=2'b10,
s4=2'b11;
reg [1:0] currentstate;
always@(posedge clk_1hz or posedge reset)
begin
if(reset)
currentstate=s1;
else
begin
case(currentstate)
s1:currentstate<=s2;
s2:currentstate<=s3;
s3:currentstate<=s4;
s4:currentstate<=s1;
default:currentstate<=s1;
endcase
end
end
always@(currentstate)
begin
case(currentstate)
s1:begin led1=0;led2=0;led3=0;end
s2:begin led1=1;led2=0;led3=0;end
s3:begin led1=0;led2=1;led3=0;end
s4:begin led1=0;led2=0;led3=1;end
default:begin led1=0;led2=0;led3=0;end
endcase
end
endmodule |
楼主
标题置顶
标题高亮
