verilog四位计数器求解

只看该作者 · 2012-6-7 12:35

本帖最后由 wdliming 于 2012-6-7 12:37 编辑

小弟verilog用编译了一个四位计数器0~9999的，可是运行的结果有问题，在每当到9,10,11的时候（即每当进位的时候），数码管的动作如下：
0009-0000-0010-0011，不知道如何解决啊？哪位高手指点一下啊？？谢谢
代码：
/*
file name  :  led4_cnt.v(for 4-bit)
author  : LiMing
date  : 2012/06/07
description :  Light one bit 7-segment and display 0 1 2 ... e f. in every constant time
fpga  : Cyclone III EP3C16F484C6
board  : DE0 (ter-asic Ltd.)
successful!!! in DE0 board
unsigned char code[]=
{
0x40, 0x79, 0x24,
0x30, 0x19, 0x12,
0x02, 0x78, 0x00,
0x10, 0x08, 0x03,
0x46, 0x21, 0x06,
0x0e
};
*/
module led4_cnt(clk_50, sega7, segb7, segc7, segd7);

input clk_50;
output [7:0] sega7;
reg [7:0] sega7;
output [7:0] segb7;
reg [7:0] segb7;
output [7:0] segc7;
reg [7:0] segc7;
output [7:0] segd7;
reg [7:0] segd7;

reg clk1k; //frequency division //1khz
reg clk1hz; //second clk signal

reg [14:0]  count_1khz; //count for frequency division
//reg [24:0] count_1hz;
reg [8:0] count_1hz;

reg [3:0]  num_ge;
reg [3:0] num_shi;
reg [3:0] num_bai;
reg [3:0] num_qian;

parameter time_limited_1khz = 15'd25_000;
//parameter time_limited_1hz = 25'd25_000_000;
parameter time_limited_1hz = 9'd500;

initial
  begin
sega7 <= 8'b0100_0000;
segb7 <= 8'b0111_1001;
segc7 <= 8'b0010_0100;
segd7 <= 8'b0011_0000;
num_ge = 4'd0;
num_shi = 4'd0;
num_bai = 4'd0;
num_qian = 4'd0;
clk1k = 1'd0;
clk1hz = 1'd0;
  end

//分频电时钟模块路 generate 1khz
always @ (posedge clk_50)//50M-1k,50M/1k/2//分频,50Mhz~1khz,占空比50%
  begin
if(count_1khz == time_limited_1khz)
begin
   clk1k <= ~clk1k;
   count_1khz <= 0;
end
else
count_1khz <= count_1khz + 1'd1;
  end

//分频电时钟模块路 generate 1hz
/*
always @(posedge clk_50)//50M-1hHz,50M/1Hz/2//分频,50Mhz~1khz,占空比50%
  begin
if(count_1hz == time_limited_1hz)
begin
   clk1hz <= ~clk1hz;
   count_1hz <= 0;
end
else
count_1hz <= count_1hz + 1'd1;
  end
  */
//分频电时钟模块路 generate 1hz
always @(posedge clk1k)//1kHz~1Hz,50M/1Hz/2//分频,50Mhz~1khz,占空比50%
  begin
if(count_1hz == time_limited_1hz)
begin
   clk1hz <= ~clk1hz;
   count_1hz <= 0;
end
else
count_1hz <= count_1hz + 1'd1;
  end
  /*
if(count == time_limited_1hz)
begin
   clk1hz <= ~clk1hz;
   count <= 0;
end
else
count <= count + 1'b1;
  */
//
always @(posedge clk1hz)
  begin
//if(num_ge==4'd10 && num_shi<4'd10)
if(num_ge==4'd10)
begin
   num_ge <= 4'd0;
   num_shi <= num_shi + 4'd1;
end

//else if(num_shi==4'd10 && num_bai<4'd10)
else if(num_shi==4'd10)
begin
   num_shi <= 4'd0;
   num_bai <= num_bai + 4'd1;
end
//else if(num_bai==4'd10 && num_qian<4'd10)
else if(num_bai==4'd10)
begin
   num_bai <= 4'd0;
   num_qian <= num_qian + 4'd1;
end
else if(num_qian==4'd10 && num_bai==4'd9 && num_shi==4'd9 && num_ge==4'd9)
begin
   num_ge <= 4'd0;
   num_shi <= 4'd0;
   num_bai <= 4'd0;
   num_qian <= 4'd0;
end
else
begin
   num_ge <= num_ge + 4'd1;
end
  end

/*always @(posedge clk_50)
  begin
if(count < time_limited)
begin
   count <= count + 1'b1;
   flag = 1'b0;
end
else
begin
   count = 24'd0;
   flag = 1'b1;
end
  end

always @(posedge flag)
  begin
if (num < 4'hf)
num <= num + 1'b1;
else
num <= 4'd0;
  end
*/

//display ge wei
always @(num_ge)
  begin
case(num_ge)
4'h0: sega7 = 8'b0100_0000;
4'h1: sega7 = 8'b0111_1001; // ---a---- 0x40
4'h2: sega7 = 8'b0010_0100; // |    | 0x70
4'h3: sega7 = 8'b0011_0000; // f    b    0x24
4'h4: sega7 = 8'b0001_1001; // |    | 0x30
4'h5: sega7 = 8'b0001_0010; // ---g---- 0x19
4'h6: sega7 = 8'b0000_0010; // |    |    0x12
4'h7: sega7 = 8'b0111_1000; // e    c    0x02
4'h8: sega7 = 8'b0000_0000; // |    |    0x78
4'h9: sega7 = 8'b0001_0000; // ---d----. 0x00
/*4'ha: sega7 = 8'b0001_0000; // 0x10
4'hb: sega7 = 8'b0000_1000; // 0x08
4'hc: sega7 = 8'b0000_0011; // 0x03
4'hd: sega7 = 8'b0100_0110; // 0x46
4'he: sega7 = 8'b0010_0001; // 0x21
4'hf: sega7 = 8'b0000_0110; // 0x06*/
default: sega7 = 8'b0100_0000; // 0x40
endcase
  end

//display shi wei
always @(num_shi)
  begin
case(num_shi)
4'h0: segb7 = 8'b0100_0000;
4'h1: segb7 = 8'b0111_1001; // ---a---- 0x40
4'h2: segb7 = 8'b0010_0100; // |    | 0x70
4'h3: segb7 = 8'b0011_0000; // f    b    0x24
4'h4: segb7 = 8'b0001_1001; // |    | 0x30
4'h5: segb7 = 8'b0001_0010; // ---g---- 0x19
4'h6: segb7 = 8'b0000_0010; // |    |    0x12
4'h7: segb7 = 8'b0111_1000; // e    c    0x02
4'h8: segb7 = 8'b0000_0000; // |    |    0x78
4'h9: segb7 = 8'b0001_0000; // ---d----. 0x00
default: segb7 = 8'b0100_0000; // 0x40
endcase
  end
//display bai wei
always @(num_bai)
  begin
case(num_bai)
4'h0: segc7 = 8'b0100_0000;
4'h1: segc7 = 8'b0111_1001; // ---a---- 0x40
4'h2: segc7 = 8'b0010_0100; // |    | 0x70
4'h3: segc7 = 8'b0011_0000; // f    b    0x24
4'h4: segc7 = 8'b0001_1001; // |    | 0x30
4'h5: segc7 = 8'b0001_0010; // ---g---- 0x19
4'h6: segc7 = 8'b0000_0010; // |    |    0x12
4'h7: segc7 = 8'b0111_1000; // e    c    0x02
4'h8: segc7 = 8'b0000_0000; // |    |    0x78
4'h9: segc7 = 8'b0001_0000; // ---d----. 0x00
default: segc7 = 8'b0100_0000; // 0x40
endcase
  end
//display qian wei
always @(num_qian)
  begin
case(num_qian)
4'h0: segd7 = 8'b0100_0000;
4'h1: segd7 = 8'b0111_1001; // ---a---- 0x40
4'h2: segd7 = 8'b0010_0100; // |    | 0x70
4'h3: segd7 = 8'b0011_0000; // f    b    0x24
4'h4: segd7 = 8'b0001_1001; // |    | 0x30
4'h5: segd7 = 8'b0001_0010; // ---g---- 0x19
4'h6: segd7 = 8'b0000_0010; // |    |    0x12
4'h7: segd7 = 8'b0111_1000; // e    c    0x02
4'h8: segd7 = 8'b0000_0000; // |    |    0x78
4'h9: segd7 = 8'b0001_0000; // ---d----. 0x00
default: segd7 = 8'b0100_0000; // 0x40
endcase
  end
endmodule