我的固件程序将EP6设置为512大小，3重缓冲，8bit，IN方向，bulk传输，FLAGB（满标志位）低电平有效。现在的现象时，我用FPGA模拟一个激励，是从00000000~11111111依次加1循环。我用的是通用驱动程序，板子上有E2PROM，当打开USB console的时候显示如下
EZ-USB interface显示如下：
点击bulk trans 按钮，屏幕中打印出顺序的数据，可以判断此时PC接收到了来自FPGA的数据，但是此时FLAGB变为低电平（FLAGB为满标志位，低电平有效）。我很好奇，我设置的端点模式是AUTO IN,为什么FLAGB还会变为低电平呢？此外，bulk 传输时只有我在点击按钮的时候才传输，还是一直在传输？
还有一个疑问，就是我设置的位宽为8bit，即FD[7:0]，软件上打印出来的数是01 FF 02 FF 03 FF...这是为什么呢？
一下是我的TD_Init（）函数中的配置：
void TD_Init(void) // Called once at startup
{
IFCONFIG = 0x03; // use IFCLK pin driven by external logic (5MHz to 48MHz)
// use slave FIFO interface pins driven sync by external master
SYNCDELAY;
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
EP6CFG = 0xE3; // sets EP6 valid for IN
// and define the endpoint for 512 byte packe
SYNCDELAY;
FIFORESET = 0x80; //reset all FIFOS
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x84;
SYNCDELAY;
FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x88;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x0D; // lets the EZ-USB auto commit IN packet
SYNCDELAY; // gives the ability to send zero length packets
// sets the slave FIFO interface to 16-bit
PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
SYNCDELAY ; // FLAGB as full flag, as pointed to by FIFOADR[1:0]
PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
SYNCDELAY; // won't generally need FLAGD
PORTACFG = 0x40; // config the PA7 pin as SLCS
SYNCDELAY;
FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low
SYNCDELAY;
EP6AUTOINLENH = 0x02; // EZ-USB automatically commits data in 512-byte chunks
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
} |
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