使用了sp6的PLL，三个输出时钟。提示如下：
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections: Unroutable signal: Inst_Sys_Ctrl/Inst_pll/dcm_sp_inst_ML_NEW_O pin: Inst_Sys_Ctrl/Inst_pll/dcm_sp_inst/CLKFB Unroutable signal: Inst_Sys_Ctrl/Inst_pll/dcm_sp_inst_ML_NEW_DIVCLK pin: Inst_Sys_Ctrl/Inst_pll/dcm_sp_inst/CLKIN |
|
楼主
