1.The Always Construct that describes the state machine is clocked.
2.All assignments to the signal or variable that represents the state machine are within the Always Construct.
3.The state machine has more than two states.
4.The state register is not used as an output of the module.
5.The state transition logic does not use arithmetic operators. For example, this condition is not met if the state transition logic uses the expression next_state <= state + 1;, which contains the arithmetic operator +. |
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