7# Backkom80
以这个为例，是Vsync_pos_cnt到Vsync_edge_tmp的delay，代码如下：
always @(posedge iClk_flag)
if((~reset_mode1) || dvi_break_notice1)
begin
iVsync_delay1 <= 1'b1;
iVsync_delay2 <= 1'b1;
iVsync_delay3 <= 1'b1;
iVsync_delay4 <= 1'b1;
end
else
begin
iVsync_delay1 <= iTFP403_VSYNC;
iVsync_delay2 <= iVsync_delay1;
iVsync_delay3 <= iVsync_delay2;
iVsync_delay4 <= iVsync_delay3;
end
assign iVsync_posedge = (~iVsync_delay4) && iVsync_delay3;
assign iVsync_negedge = iVsync_delay4 && (~iVsync_delay3);
always @(posedge iClk_flag)
if((~reset_mode1) || dvi_break_notice1)
Vsync_edge_state <= 4'b0000;
else
case(Vsync_edge_state)
4'b0000 : begin
if(iVsync_posedge)
Vsync_edge_state <= 4'b0001;
else
Vsync_edge_state <= 4'b0000;
end
4'b0001 : begin
if(iVsync_negedge)
Vsync_edge_state <= 4'b0010;
else
Vsync_edge_state <= 4'b0001;
end
4'b0010 : begin
if(iVsync_posedge)
Vsync_edge_state <= 4'b0100;
else
Vsync_edge_state <= 4'b0010;
end
4'b0100 : begin
if(iVsync_negedge)
Vsync_edge_state <= 4'b0000;
else
Vsync_edge_state <= 4'b0100;
end
default : begin
Vsync_edge_state <= 4'b0000;
end
endcase
always @(posedge iClk_flag)
if((~reset_mode1) || dvi_break_notice1)
begin
Vsync_pos_cnt <= 32'd0;
end
else
if(Vsync_edge_state == 4'b0001)
Vsync_pos_cnt <= Vsync_pos_cnt + 1;
else if(Vsync_edge_state == 4'b0010)
Vsync_pos_cnt <= Vsync_pos_cnt;
else
Vsync_pos_cnt <= 32'd0;
always @(posedge iClk_flag)
if((~reset_mode1) || dvi_break_notice1)
begin
Vsync_neg_cnt <= 32'd0;
end
else
if(Vsync_edge_state == 4'b0010)
Vsync_neg_cnt <= Vsync_neg_cnt + 1;
else
Vsync_neg_cnt <= 32'd0;
reg Vsync_edge_tmp;
always @(posedge iClk_flag)
if((~reset_mode1) || dvi_break_notice1)
Vsync_edge_tmp <= 1'b0;
else
if((Vsync_edge_state == 4'b0010) && iVsync_posedge)
if(Vsync_neg_cnt > Vsync_pos_cnt)
Vsync_edge_tmp <= 1'b1;
else
Vsync_edge_tmp <= 1'b0;
else
Vsync_edge_tmp <= Vsync_edge_tmp;
从报告中我知道是0到31阶的进位链造成了这么大的delay，但是采用何种措施来降低这些delay，没有思路。请大家指教！
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