verilog任意整数分频的[url=]代码[/url]：
module clk3(clk,rst_n,clkout);
input clk;
input rst_n;
output clkout;
parameter N = 3;
reg clk_n,clk_p;
reg[3:0] cnt_n,cnt_p;
assign clkout =(N ==1)? clk : ( (N[0]==0)? clk_p:(clk_p |clk_n )) ;
always@(posedge clk)begin
if(!rst_n)
cnt_p <= 0;
else begin
if(cnt_p == N-1)
cnt_p <= 0;
else
cnt_p <= cnt_p +1;
end
end
always@(posedge clk)begin
if(!rst_n)
clk_p <= 0;
else begin
if(cnt_p <= (N>>1))
clk_p <= 0;
else
clk_p <= 1;
end
end
always@(negedge clk)begin
if(!rst_n)
cnt_n <= 0;
else begin
if(cnt_n == N-1)
cnt_n <= 0;
else
cnt_n <= cnt_n + 1;
end
end
always@(negedge clk)begin
if(!rst_n)
clk_n <= 0;
else begin
if(cnt_n <= (N>>1))
clk_n <= 0;
else
clk_n <= 1;
end
end
endmodule |
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