本帖最后由 seavend0603 于 2012-12-2 14:59 编辑
我用的是芯片XC3S 250E VQ100 封装的，其中90，91都是GCLK引脚，90引脚可以作为时钟输入，91作为时钟输入时就报错，其中是这么定义引脚的：NET "clkin" loc = P91;
报错信息为：
A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <clkin_BUFGP/BUFG> is placed at site <BUFGMUX_X1Y0>. The IO component <clkin> is
placed at site <P91>. This will not allow the use of the fast path between the IO and the Clock buffer. If this sub
optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
demote this message to a WARNING and allow your design to continue. However, the use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used
directly in the .ucf file to override this clock rule.
< NET "clkin" CLOCK_DEDICATED_ROUTE = FALSE; >
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