看到了争做X-Man，赢取赛灵思FPGA“X-MAN荣誉勋章”，所以俺这个菜鸟也来分享一下吧！
资料也可以的，那我就分享一个我自己写的基于VGA汉字显示的VHDL程序。。
看一看吧！！！
这是在VGA上的四个汉字显示，是我的学校名字！！！
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vga is
port(clk,rst : in std_logic;
r,g,b : out std_logic;
hs,vs : out std_logic
);
end vga;
architecture beha of vga is
signal clk_25M:std_logic:='1';
signal hclk:integer range 0 to 1000:=0;
signal vclk:integer range 0 to 1000:=0;
signal hs1:std_logic:='0';
signal vs1:std_logic:='0';
signal r1:std_logic:='1';
signal g1:std_logic:='1';
signal b1:std_logic:='1';
signal r2:std_logic:='1';
signal g2:std_logic:='1';
signal b2:std_logic:='1';
type data_buffer is array(0 to 127) of std_logic_vector(7 downto 0);
constant buf:data_buffer:=(
x"02",x"04",x"E4",x"21",x"02",x"80",x"88",x"88",x"84",x"84",x"E3",x"02",x"02",x"82",x"42",x"32",
x"02",x"04",x"7F",x"20",x"1C",x"03",x"00",x"3F",x"08",x"08",x"7F",x"00",x"08",x"10",x"20",x"20",---0
x"10",x"10",x"10",x"10",x"10",x"32",x"52",x"52",x"11",x"10",x"10",x"08",x"08",x"04",x"04",x"02",
x"20",x"21",x"21",x"21",x"23",x"25",x"25",x"29",x"29",x"21",x"21",x"21",x"21",x"21",x"21",x"20",---1
x"80",x"08",x"30",x"10",x"FE",x"02",x"F1",x"00",x"00",x"FE",x"00",x"00",x"00",x"00",x"40",x"80",
x"10",x"31",x"13",x"09",x"7F",x"20",x"17",x"02",x"01",x"7F",x"01",x"01",x"01",x"01",x"01",x"00",---2
x"00",x"1F",x"F1",x"29",x"05",x"C5",x"09",x"11",x"F1",x"95",x"89",x"81",x"41",x"41",x"21",x"11",
x"01",x"02",x"7F",x"20",x"00",x"1F",x"00",x"00",x"7F",x"04",x"04",x"04",x"44",x"44",x"44",x"78"---3
);
begin
process(clk)
begin
if clk'event and clk='1' then
clk_25M<= not clk_25M;
end if;
end process;
process(rst,clk_25M)
begin
if clk_25M'event and clk_25M='1' then
if(hclk=800) then hclk<=0;
else hclk<=hclk+1;
end if;
if hclk>=656 and hclk<752 then hs1<='0';
else hs1<='1';
end if;
end if;
end process;
process(rst,hs1)
variable cnt :integer range 0 to 1000 :=0;
begin
if hs1'event and hs1='0' then
if vclk=524 then vclk<=0;
else vclk<=vclk+1;
end if;
if vclk >= 491 and vclk<492 then
vs1<='0';
else vs1<='1';
end if;
end if;
end process;
process(clk,vclk,hclk)
begin
if clk'event and clk='1' then
if vclk>=100 and vclk<116 and hclk>=100 and hclk <108 then
if buf((vclk-100))(hclk-100)='1' then r2<='1';g2<='1';b2<='1';
else r2<='1';g2<='0';b2<='0';
end if;
end if;
if vclk>=100 and vclk<116 and hclk>=108 and hclk <116 then
if buf(vclk-100+16)(hclk-108)='1' then r2<='1';g2<='1';b2<='1';
else r2<='1';g2<='0';b2<='0';
end if;
end if;
if vclk>=100 and vclk<116 and hclk>=116 and hclk <124 then
if buf((vclk-100+32))(hclk-100)='1' then r2<='1';g2<='1';b2<='1';
else r2<='1';g2<='0';b2<='0';
end if;
end if;
if vclk>=100 and vclk<116 and hclk>=124 and hclk <132 then
if buf(vclk-100+48)(hclk-108)='1' then r2<='1';g2<='1';b2<='1';
else r2<='1';g2<='0';b2<='0';
end if;
end if;
if vclk>=100 and vclk<116 and hclk>=132 and hclk <140 then
if buf((vclk-100+64))(hclk-100)='1' then r2<='1';g2<='1';b2<='1';
else r2<='1';g2<='0';b2<='0';
end if;
end if;
if vclk>=100 and vclk<116 and hclk>=140 and hclk <148 then
if buf(vclk-100+80)(hclk-108)='1' then r2<='1';g2<='1';b2<='1';
else r2<='1';g2<='0';b2<='0';
end if;
end if;
if vclk>=100 and vclk<116 and hclk>=148 and hclk <156 then
if buf((vclk-100+96))(hclk-100)='1' then r2<='1';g2<='1';b2<='1';
else r2<='1';g2<='0';b2<='0';
end if;
end if;
if vclk>=100 and vclk<116 and hclk>=156 and hclk <164 then
if buf(vclk-100+112)(hclk-108)='1' then r2<='1';g2<='1';b2<='1';
else r2<='1';g2<='0';b2<='0';
end if;
end if;
end if;
end process;
r<=r1 and hs1 and vs1 and r2;
g<=g1 and hs1 and vs1 and g2;
b<=b1 and hs1 and vs1 and b2;
hs<=hs1;
vs<=vs1;
end beha;
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