#include <msp430f5310.h>
signed int ADC_Result;
void delay(void);
void int_clk()
{
WDTCTL = WDTPW+WDTHOLD; //关闭看门狗
PMAPPWD = 0x02D52; // Enable Write-access to modify port mapping registers
P4MAP7 = PM_MCLK;
PMAPPWD = 0; // Disable Write-Access to modify port mapping registers
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
// Increase Vcore setting to level1 to support fsystem=12MHz
// NOTE: Change core voltage one level at a time..
//SetVcoreUp (0x01);
// Initialize DCO to 12MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
// UCSCTL4 =0x0233;
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1DIR |= BIT0; // Set P1.0 to output direction
int_clk();
// Configure ADC
while(REFCTL0 & REFGENBUSY); // If ref generator busy, WAIT
REFCTL0 |= REFVSEL_2+REFON; // Select internal ref = 2.5V
ADC10CTL0 |= ADC10SHT_2 + ADC10ON; // ADC10ON, S&H=16 ADC clks
ADC10CTL1 |= ADC10SHP+ ADC10CONSEQ_0; // ADCCLK = MODOSC; sampling timer
ADC10CTL2 |= ADC10RES; // + ADC10DF // 10-bit conv result; signed format
ADC10MCTL0 |= ADC10INCH_0+ADC10SREF_1; // A0 ADC input select; Vref=AVCC
// ADC10IE |= ADC10IE0; // Enable ADC conv complete interrupt
__bis_SR_register(GIE);
for (;;)
{
__delay_cycles(5000);
ADC10CTL0 |= ADC10ENC + ADC10SC; // Sampling and conversion start
//__bis_SR_register(CPUOFF + GIE); // LPM0, ADC10_ISR will force exit
while (ADC10CTL1 & ADC10BUSY);
ADC_Result = (int)ADC10MEM0;
__no_operation(); // For debug only
if (ADC_Result < 0)
P1OUT &= ~BIT0; // Clear P1.0 LED off
else
P1OUT |= BIT0; // Set P1.0 LED on
}
|
楼主
