时序问题请教！！

只看该作者 · 2013-4-8 16:56

本帖最后由 cxh_boy 于 2013-4-9 09:58 编辑

系统时钟是5.7ns  ,两级reg之间延迟达到 3ns ,迷惑！！！请大家指教！！

//counter :
always@(posedge SYSCLK or negedge RST_B)
if(!RST_B)
COUNTER <= 4'h0 ;
else
COUNTER <= `UD COUNTER_N ;

assign COUNTER_N = (COUNTER == 4'd13)? 4'h0 : COUNTER + 1'h1 ;
//Send Data :
always@(posedge SYSCLK or negedge RST_B)
if(!RST_B)
DATA_10BIT_OUT <= `UD 10'h0 ;
else
DATA_10BIT_OUT <= `UD DATA_10BIT_OUT_N ;
always@(*)
begin
case(COUNTER)
4'd0 :  DATA_10BIT_OUT_N = {1'h0,
                           VIDEO_7BIT_IN_REG_7[1] ,
                           VIDEO_7BIT_IN_REG_7[0] ,

                           VIDEO_7BIT_IN_0[6] ,
                           VIDEO_7BIT_IN_0[5] ,
                           VIDEO_7BIT_IN_0[4] ,
                           VIDEO_7BIT_IN_0[3] ,
                           VIDEO_7BIT_IN_0[2] ,
                           VIDEO_7BIT_IN_0[1] ,
                           VIDEO_7BIT_IN_0[0]
                           };

4'd1 :  DATA_10BIT_OUT_N = {1'h0,
                           VIDEO_7BIT_IN_REG_7[3] ,
                           VIDEO_7BIT_IN_REG_7[2] ,

                           VIDEO_7BIT_IN_1[6] ,
                           VIDEO_7BIT_IN_1[5] ,
                           VIDEO_7BIT_IN_1[4] ,
                           VIDEO_7BIT_IN_1[3] ,
                           VIDEO_7BIT_IN_1[2] ,
                           VIDEO_7BIT_IN_1[1] ,
                           VIDEO_7BIT_IN_1[0]
                           };


4'd2 :  DATA_10BIT_OUT_N = {1'h0,
                           VIDEO_7BIT_IN_REG_7[5] ,
                           VIDEO_7BIT_IN_REG_7[4] ,

                           VIDEO_7BIT_IN_2[6] ,
                           VIDEO_7BIT_IN_2[5] ,
                           VIDEO_7BIT_IN_2[4] ,
                           VIDEO_7BIT_IN_2[3] ,
                           VIDEO_7BIT_IN_2[2] ,
                           VIDEO_7BIT_IN_2[1] ,
                           VIDEO_7BIT_IN_2[0]
                           };

4'd3 :  DATA_10BIT_OUT_N = {1'h0,
                           DATA_485_IN       ,
                           VIDEO_7BIT_IN_REG_7[6] ,

                           VIDEO_7BIT_IN_3[6] ,
                           VIDEO_7BIT_IN_3[5] ,
                           VIDEO_7BIT_IN_3[4] ,
                           VIDEO_7BIT_IN_3[3] ,
                           VIDEO_7BIT_IN_3[2] ,
                           VIDEO_7BIT_IN_3[1] ,
                           VIDEO_7BIT_IN_3[0]
                           };

4'd4 :  DATA_10BIT_OUT_N = {1'h0,
                           1'h1,
                           1'h0,
                           VIDEO_7BIT_IN_4[6] ,
                           VIDEO_7BIT_IN_4[5] ,
                           VIDEO_7BIT_IN_4[4] ,
                           VIDEO_7BIT_IN_4[3] ,
                           VIDEO_7BIT_IN_4[2] ,
                           VIDEO_7BIT_IN_4[1] ,
                           VIDEO_7BIT_IN_4[0]
                           };

4'd5 :  DATA_10BIT_OUT_N = {1'h0,
                           1'h1,
                           1'h0,
                           VIDEO_7BIT_IN_5[6] ,
                           VIDEO_7BIT_IN_5[5] ,
                           VIDEO_7BIT_IN_5[4] ,
                           VIDEO_7BIT_IN_5[3] ,
                           VIDEO_7BIT_IN_5[2] ,
                           VIDEO_7BIT_IN_5[1] ,
                           VIDEO_7BIT_IN_5[0]
                           };

4'd6 :  DATA_10BIT_OUT_N = {1'h0,
                           1'h1,
                           1'h0,
                           VIDEO_7BIT_IN_6[6] ,
                           VIDEO_7BIT_IN_6[5] ,
                           VIDEO_7BIT_IN_6[4] ,
                           VIDEO_7BIT_IN_6[3] ,
                           VIDEO_7BIT_IN_6[2] ,
                           VIDEO_7BIT_IN_6[1] ,
                           VIDEO_7BIT_IN_6[0]
                           };
//-----------second 8v------------
4'd7 :  DATA_10BIT_OUT_N = {1'h0,
                           VIDEO_7BIT_IN_REG_15[1],
                           VIDEO_7BIT_IN_REG_15[0],

                           VIDEO_7BIT_IN_8[6] ,
                           VIDEO_7BIT_IN_8[5] ,
                           VIDEO_7BIT_IN_8[4] ,
                           VIDEO_7BIT_IN_8[3] ,
                           VIDEO_7BIT_IN_8[2] ,
                           VIDEO_7BIT_IN_8[1] ,
                           VIDEO_7BIT_IN_8[0]
                           };
4'd8 :  DATA_10BIT_OUT_N = {1'h0,
                           VIDEO_7BIT_IN_REG_15[3],
                           VIDEO_7BIT_IN_REG_15[2],

                           VIDEO_7BIT_IN_9[6] ,
                           VIDEO_7BIT_IN_9[5] ,
                           VIDEO_7BIT_IN_9[4] ,
                           VIDEO_7BIT_IN_9[3] ,
                           VIDEO_7BIT_IN_9[2] ,
                           VIDEO_7BIT_IN_9[1] ,
                           VIDEO_7BIT_IN_9[0]
                           };
4'd9 :  DATA_10BIT_OUT_N = {1'h0,
                           VIDEO_7BIT_IN_REG_15[5],
                           VIDEO_7BIT_IN_REG_15[4],

                           VIDEO_7BIT_IN_10[6] ,
                           VIDEO_7BIT_IN_10[5] ,
                           VIDEO_7BIT_IN_10[4] ,
                           VIDEO_7BIT_IN_10[3] ,
                           VIDEO_7BIT_IN_10[2] ,
                           VIDEO_7BIT_IN_10[1] ,
                           VIDEO_7BIT_IN_10[0]
                           };

4'd10 :  DATA_10BIT_OUT_N ={1'h0,
                           1'h1,
                           VIDEO_7BIT_IN_REG_15[6] ,

                           VIDEO_7BIT_IN_11[6] ,
                           VIDEO_7BIT_IN_11[5] ,
                           VIDEO_7BIT_IN_11[4] ,
                           VIDEO_7BIT_IN_11[3] ,
                           VIDEO_7BIT_IN_11[2] ,
                           VIDEO_7BIT_IN_11[1] ,
                           VIDEO_7BIT_IN_11[0]
                           };
4'd11 :  DATA_10BIT_OUT_N ={1'h0,
                           1'h1,
                           1'h0,
                           VIDEO_7BIT_IN_12[6] ,
                           VIDEO_7BIT_IN_12[5] ,
                           VIDEO_7BIT_IN_12[4] ,
                           VIDEO_7BIT_IN_12[3] ,
                           VIDEO_7BIT_IN_12[2] ,
                           VIDEO_7BIT_IN_12[1] ,
                           VIDEO_7BIT_IN_12[0]
                           };
4'd12 :  DATA_10BIT_OUT_N ={1'h0,
                           1'h1,
                           1'h0,
                           VIDEO_7BIT_IN_13[6] ,
                           VIDEO_7BIT_IN_13[5] ,
                           VIDEO_7BIT_IN_13[4] ,
                           VIDEO_7BIT_IN_13[3] ,
                           VIDEO_7BIT_IN_13[2] ,
                           VIDEO_7BIT_IN_13[1] ,
                           VIDEO_7BIT_IN_13[0]
                           };
4'd13 :  DATA_10BIT_OUT_N ={1'h1,
                           1'h1,
                           1'h0,
                           VIDEO_7BIT_IN_14[6] ,
                           VIDEO_7BIT_IN_14[5] ,
                           VIDEO_7BIT_IN_14[4] ,
                           VIDEO_7BIT_IN_14[3] ,
                           VIDEO_7BIT_IN_14[2] ,
                           VIDEO_7BIT_IN_14[1] ,
                           VIDEO_7BIT_IN_14[0]
                           };
default : DATA_10BIT_OUT_N = DATA_10BIT_OUT  ;
endcase
end
上面是代码,下面是timequest的时序分析报错：
Slack                   From Node                                                                   To Node                                                                            Lanuch  Clock       LatchClock
-3.503  DATA_CONNECT ：DATA_CONNECT_MY|COUNTER[1] DATA_CONNECT：DATA_CONNECT_MY|DATA_10BIT_OUT[3]       SYSCLK                SYSCLK

只看该作者 · 2013-4-8 21:03

分析一下超标的路径, 看看延时在各段分布情况. 就可以找到原因.

我大致看了下, DATA_10BIT_OUT_N的输入逻辑太复杂了.
可以把每个case分支都赋给一个reg, 采用寄存器方式. 然后延时一时钟, 直接赋给DATA_10BIT_OUT.

always@(posedge SYSCLK or negedge RST_B)
begin
if(!RST_B) begin
DATA_10BIT_OUT <= 0;
DATA_10BIT_OUT_LIST[0] <= 0;
DATA_10BIT_OUT_LIST[1] <= 0;
DATA_10BIT_OUT_LIST[2] <= 0;
DATA_10BIT_OUT_LIST[3] <= 0;
DATA_10BIT_OUT_LIST[4] <= 0;
DATA_10BIT_OUT_LIST[5] <= 0;
DATA_10BIT_OUT_LIST[6] <= 0;
DATA_10BIT_OUT_LIST[7] <= 0;
DATA_10BIT_OUT_LIST[8] <= 0;
DATA_10BIT_OUT_LIST[9] <= 0;
DATA_10BIT_OUT_LIST[10] <= 0;
DATA_10BIT_OUT_LIST[11] <= 0;
DATA_10BIT_OUT_LIST[12] <= 0;
DATA_10BIT_OUT_LIST[13] <= 0;
end
else begin

DATA_10BIT_OUT_LIST[0] <= {1'h0,
VIDEO_7BIT_IN_REG_7[1] ,
VIDEO_7BIT_IN_REG_7[0] ,

VIDEO_7BIT_IN_0[6] ,
VIDEO_7BIT_IN_0[5] ,
VIDEO_7BIT_IN_0[4] ,
VIDEO_7BIT_IN_0[3] ,
VIDEO_7BIT_IN_0[2] ,
VIDEO_7BIT_IN_0[1] ,
VIDEO_7BIT_IN_0[0]
};

DATA_10BIT_OUT_LIST[1] <= {1'h0,
VIDEO_7BIT_IN_REG_7[3] ,
VIDEO_7BIT_IN_REG_7[2] ,

VIDEO_7BIT_IN_1[6] ,
VIDEO_7BIT_IN_1[5] ,
VIDEO_7BIT_IN_1[4] ,
VIDEO_7BIT_IN_1[3] ,
VIDEO_7BIT_IN_1[2] ,
VIDEO_7BIT_IN_1[1] ,
VIDEO_7BIT_IN_1[0]
};

DATA_10BIT_OUT_LIST[2] <= {1'h0,
VIDEO_7BIT_IN_REG_7[5] ,
VIDEO_7BIT_IN_REG_7[4] ,

VIDEO_7BIT_IN_2[6] ,
VIDEO_7BIT_IN_2[5] ,
VIDEO_7BIT_IN_2[4] ,
VIDEO_7BIT_IN_2[3] ,
VIDEO_7BIT_IN_2[2] ,
VIDEO_7BIT_IN_2[1] ,
VIDEO_7BIT_IN_2[0]
};
DATA_10BIT_OUT_LIST[3] <= {1'h0,
DATA_485_IN       ,
VIDEO_7BIT_IN_REG_7[6] ,

VIDEO_7BIT_IN_3[6] ,
VIDEO_7BIT_IN_3[5] ,
VIDEO_7BIT_IN_3[4] ,
VIDEO_7BIT_IN_3[3] ,
VIDEO_7BIT_IN_3[2] ,
VIDEO_7BIT_IN_3[1] ,
VIDEO_7BIT_IN_3[0]};
DATA_10BIT_OUT_LIST[4] <= {1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_4[6] ,
VIDEO_7BIT_IN_4[5] ,
VIDEO_7BIT_IN_4[4] ,
VIDEO_7BIT_IN_4[3] ,
VIDEO_7BIT_IN_4[2] ,
VIDEO_7BIT_IN_4[1] ,
VIDEO_7BIT_IN_4[0]
};

DATA_10BIT_OUT_LIST[5] <= {1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_5[6] ,
VIDEO_7BIT_IN_5[5] ,
VIDEO_7BIT_IN_5[4] ,
VIDEO_7BIT_IN_5[3] ,
VIDEO_7BIT_IN_5[2] ,
VIDEO_7BIT_IN_5[1] ,
VIDEO_7BIT_IN_5[0]
};

DATA_10BIT_OUT_LIST[6] <= {1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_6[6] ,
VIDEO_7BIT_IN_6[5] ,
VIDEO_7BIT_IN_6[4] ,
VIDEO_7BIT_IN_6[3] ,
VIDEO_7BIT_IN_6[2] ,
VIDEO_7BIT_IN_6[1] ,
VIDEO_7BIT_IN_6[0]
};
DATA_10BIT_OUT_LIST[7] <= {1'h0,
VIDEO_7BIT_IN_REG_15[1],
VIDEO_7BIT_IN_REG_15[0],

VIDEO_7BIT_IN_8[6] ,
VIDEO_7BIT_IN_8[5] ,
VIDEO_7BIT_IN_8[4] ,
VIDEO_7BIT_IN_8[3] ,
VIDEO_7BIT_IN_8[2] ,
VIDEO_7BIT_IN_8[1] ,
VIDEO_7BIT_IN_8[0]
};

DATA_10BIT_OUT_LIST[8] <= {1'h0,
VIDEO_7BIT_IN_REG_15[3],
VIDEO_7BIT_IN_REG_15[2],

VIDEO_7BIT_IN_9[6] ,
VIDEO_7BIT_IN_9[5] ,
VIDEO_7BIT_IN_9[4] ,
VIDEO_7BIT_IN_9[3] ,
VIDEO_7BIT_IN_9[2] ,
VIDEO_7BIT_IN_9[1] ,
VIDEO_7BIT_IN_9[0]
};

DATA_10BIT_OUT_LIST[9] <= {1'h0,
VIDEO_7BIT_IN_REG_15[5],
VIDEO_7BIT_IN_REG_15[4],

VIDEO_7BIT_IN_10[6] ,
VIDEO_7BIT_IN_10[5] ,
VIDEO_7BIT_IN_10[4] ,
VIDEO_7BIT_IN_10[3] ,
VIDEO_7BIT_IN_10[2] ,
VIDEO_7BIT_IN_10[1] ,
VIDEO_7BIT_IN_10[0]
};

DATA_10BIT_OUT_LIST[10] <={1'h0,
1'h1,
VIDEO_7BIT_IN_REG_15[6] ,

VIDEO_7BIT_IN_11[6] ,
VIDEO_7BIT_IN_11[5] ,
VIDEO_7BIT_IN_11[4] ,
VIDEO_7BIT_IN_11[3] ,
VIDEO_7BIT_IN_11[2] ,
VIDEO_7BIT_IN_11[1] ,
VIDEO_7BIT_IN_11[0]
};
DATA_10BIT_OUT_LIST[11] <={1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_12[6] ,
VIDEO_7BIT_IN_12[5] ,
VIDEO_7BIT_IN_12[4] ,
VIDEO_7BIT_IN_12[3] ,
VIDEO_7BIT_IN_12[2] ,
VIDEO_7BIT_IN_12[1] ,
VIDEO_7BIT_IN_12[0]
};

DATA_10BIT_OUT_LIST[12] <={1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_13[6] ,
VIDEO_7BIT_IN_13[5] ,
VIDEO_7BIT_IN_13[4] ,
VIDEO_7BIT_IN_13[3] ,
VIDEO_7BIT_IN_13[2] ,
VIDEO_7BIT_IN_13[1] ,
VIDEO_7BIT_IN_13[0]
};
DATA_10BIT_OUT_LIST[13] <={1'h1,
1'h1,
1'h0,
VIDEO_7BIT_IN_14[6] ,
VIDEO_7BIT_IN_14[5] ,
VIDEO_7BIT_IN_14[4] ,
VIDEO_7BIT_IN_14[3] ,
VIDEO_7BIT_IN_14[2] ,
VIDEO_7BIT_IN_14[1] ,
VIDEO_7BIT_IN_14[0]
};
case(COUNTER)
4'd0 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[0];
4'd1 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[1];
4'd2 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[2];
4'd3 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[3];
4'd4 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[4];
4'd5 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[5];
4'd6 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[6];
//-----------second 8v------------
4'd7 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[7];
4'd8 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[8];
4'd9 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[9];
4'd10 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[10];
4'd11 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[11];
4'd12 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[12];
4'd13 : DATA_10BIT_OUT <= DATA_10BIT_OUT_LIST[13];
endcase

只看该作者 · 2013-4-9 09:10

延时长是肯定的
你可想像一下
这个MUX综合出来会多么复杂
建议从整个系统入手
把这一块算法简化一下

只看该作者 · 2013-4-9 09:42

resxpl 发表于 2013-4-8 21:03
分析一下超标的路径, 看看延时在各段分布情况. 就可以找到原因.

我大致看了下, DATA_10BIT_OUT_N的输入逻 ...

谢谢 resxpl ！按你的方法我试了下,延迟降低到了1个多纳秒,不过还是没能达到要求！！不过芯片资源耗费了更多. 你说的找超标的关键路径,能不能具体说说,就是找到了应该怎么处理之内！

只看该作者 · 2013-4-9 09:46

ifpga 发表于 2013-4-9 09:10
延时长是肯定的
你可想像一下
这个MUX综合出来会多么复杂

嗯,系统其它地方没有问题,上面这些代码,是一个发射module,数据必须汇总之后发出去,刚就respxl的方法试了下,改善不少！只是还是没达标！

只看该作者 · 2013-4-9 21:04

改进方法在前面已经给出来了. 基本就是分解逻辑. 利用延迟几个周期达到提高定时性能的目的.
前面只是简单改进, 还可以使用OneHot序列.

always@(posedge SYSCLK or negedge RST_B)
if(!RST_B) begin
COUNTER_BUF <= 14'b0001 ;
COUNTER <= 0;
end
else begin
COUNTER_BUF <= `UD {COUNTER_BUF[12:0], COUNTER_BUF[13]} ;
COUNTER <= COUNTER_BUF;
end

always@(posedge SYSCLK or negedge RST_B)
begin
if(!RST_B) begin
DATA_10BIT_OUT <= 0;
DATA_10BIT_OUT_BUF[0] <= 0;
DATA_10BIT_OUT_BUF[1] <= 0;
DATA_10BIT_OUT_BUF[2] <= 0;
DATA_10BIT_OUT_BUF[3] <= 0;
DATA_10BIT_OUT_LIST[0] <= 0;
DATA_10BIT_OUT_LIST[1] <= 0;
DATA_10BIT_OUT_LIST[2] <= 0;
DATA_10BIT_OUT_LIST[3] <= 0;
DATA_10BIT_OUT_LIST[4] <= 0;
DATA_10BIT_OUT_LIST[5] <= 0;
DATA_10BIT_OUT_LIST[6] <= 0;
DATA_10BIT_OUT_LIST[7] <= 0;
DATA_10BIT_OUT_LIST[8] <= 0;
DATA_10BIT_OUT_LIST[9] <= 0;
DATA_10BIT_OUT_LIST[10] <= 0;
DATA_10BIT_OUT_LIST[11] <= 0;
DATA_10BIT_OUT_LIST[12] <= 0;
DATA_10BIT_OUT_LIST[13] <= 0;
end
else begin

DATA_10BIT_OUT_LIST[0] <= 0;
DATA_10BIT_OUT_LIST[1] <= 0;
DATA_10BIT_OUT_LIST[2] <= 0;
DATA_10BIT_OUT_LIST[3] <= 0;
DATA_10BIT_OUT_LIST[4] <= 0;
DATA_10BIT_OUT_LIST[5] <= 0;
DATA_10BIT_OUT_LIST[6] <= 0;
DATA_10BIT_OUT_LIST[7] <= 0;
DATA_10BIT_OUT_LIST[8] <= 0;
DATA_10BIT_OUT_LIST[9] <= 0;
DATA_10BIT_OUT_LIST[10] <= 0;
DATA_10BIT_OUT_LIST[11] <= 0;
DATA_10BIT_OUT_LIST[12] <= 0;
DATA_10BIT_OUT_LIST[13] <= 0;

if(COUNTER[0])
DATA_10BIT_OUT_LIST[0] <= {1'h0,
VIDEO_7BIT_IN_REG_7[1] ,
VIDEO_7BIT_IN_REG_7[0] ,

VIDEO_7BIT_IN_0[6] ,
VIDEO_7BIT_IN_0[5] ,
VIDEO_7BIT_IN_0[4] ,
VIDEO_7BIT_IN_0[3] ,
VIDEO_7BIT_IN_0[2] ,
VIDEO_7BIT_IN_0[1] ,
VIDEO_7BIT_IN_0[0]
};

if(COUNTER[1])
DATA_10BIT_OUT_LIST[1] <= {1'h0,
VIDEO_7BIT_IN_REG_7[3] ,
VIDEO_7BIT_IN_REG_7[2] ,

VIDEO_7BIT_IN_1[6] ,
VIDEO_7BIT_IN_1[5] ,
VIDEO_7BIT_IN_1[4] ,
VIDEO_7BIT_IN_1[3] ,
VIDEO_7BIT_IN_1[2] ,
VIDEO_7BIT_IN_1[1] ,
VIDEO_7BIT_IN_1[0]
};

if(COUNTER[2])
DATA_10BIT_OUT_LIST[2] <= {1'h0,
VIDEO_7BIT_IN_REG_7[5] ,
VIDEO_7BIT_IN_REG_7[4] ,

VIDEO_7BIT_IN_2[6] ,
VIDEO_7BIT_IN_2[5] ,
VIDEO_7BIT_IN_2[4] ,
VIDEO_7BIT_IN_2[3] ,
VIDEO_7BIT_IN_2[2] ,
VIDEO_7BIT_IN_2[1] ,
VIDEO_7BIT_IN_2[0]
};

if(COUNTER[3])
DATA_10BIT_OUT_LIST[3] <= {1'h0,
DATA_485_IN       ,
VIDEO_7BIT_IN_REG_7[6] ,

VIDEO_7BIT_IN_3[6] ,
VIDEO_7BIT_IN_3[5] ,
VIDEO_7BIT_IN_3[4] ,
VIDEO_7BIT_IN_3[3] ,
VIDEO_7BIT_IN_3[2] ,
VIDEO_7BIT_IN_3[1] ,
VIDEO_7BIT_IN_3[0]};

if(COUNTER[4])
DATA_10BIT_OUT_LIST[4] <= {1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_4[6] ,
VIDEO_7BIT_IN_4[5] ,
VIDEO_7BIT_IN_4[4] ,
VIDEO_7BIT_IN_4[3] ,
VIDEO_7BIT_IN_4[2] ,
VIDEO_7BIT_IN_4[1] ,
VIDEO_7BIT_IN_4[0]
};

if(COUNTER[5])
DATA_10BIT_OUT_LIST[5] <= {1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_5[6] ,
VIDEO_7BIT_IN_5[5] ,
VIDEO_7BIT_IN_5[4] ,
VIDEO_7BIT_IN_5[3] ,
VIDEO_7BIT_IN_5[2] ,
VIDEO_7BIT_IN_5[1] ,
VIDEO_7BIT_IN_5[0]
};

if(COUNTER[6])
DATA_10BIT_OUT_LIST[6] <= {1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_6[6] ,
VIDEO_7BIT_IN_6[5] ,
VIDEO_7BIT_IN_6[4] ,
VIDEO_7BIT_IN_6[3] ,
VIDEO_7BIT_IN_6[2] ,
VIDEO_7BIT_IN_6[1] ,
VIDEO_7BIT_IN_6[0]
};

if(COUNTER[7])
DATA_10BIT_OUT_LIST[7] <= {1'h0,
VIDEO_7BIT_IN_REG_15[1],
VIDEO_7BIT_IN_REG_15[0],

VIDEO_7BIT_IN_8[6] ,
VIDEO_7BIT_IN_8[5] ,
VIDEO_7BIT_IN_8[4] ,
VIDEO_7BIT_IN_8[3] ,
VIDEO_7BIT_IN_8[2] ,
VIDEO_7BIT_IN_8[1] ,
VIDEO_7BIT_IN_8[0]
};

if(COUNTER[8])
DATA_10BIT_OUT_LIST[8] <= {1'h0,
VIDEO_7BIT_IN_REG_15[3],
VIDEO_7BIT_IN_REG_15[2],

VIDEO_7BIT_IN_9[6] ,
VIDEO_7BIT_IN_9[5] ,
VIDEO_7BIT_IN_9[4] ,
VIDEO_7BIT_IN_9[3] ,
VIDEO_7BIT_IN_9[2] ,
VIDEO_7BIT_IN_9[1] ,
VIDEO_7BIT_IN_9[0]
};

if(COUNTER[9])
DATA_10BIT_OUT_LIST[9] <= {1'h0,
VIDEO_7BIT_IN_REG_15[5],
VIDEO_7BIT_IN_REG_15[4],

VIDEO_7BIT_IN_10[6] ,
VIDEO_7BIT_IN_10[5] ,
VIDEO_7BIT_IN_10[4] ,
VIDEO_7BIT_IN_10[3] ,
VIDEO_7BIT_IN_10[2] ,
VIDEO_7BIT_IN_10[1] ,
VIDEO_7BIT_IN_10[0]
};

if(COUNTER[10])
DATA_10BIT_OUT_LIST[10] <={1'h0,
1'h1,
VIDEO_7BIT_IN_REG_15[6] ,

VIDEO_7BIT_IN_11[6] ,
VIDEO_7BIT_IN_11[5] ,
VIDEO_7BIT_IN_11[4] ,
VIDEO_7BIT_IN_11[3] ,
VIDEO_7BIT_IN_11[2] ,
VIDEO_7BIT_IN_11[1] ,
VIDEO_7BIT_IN_11[0]
};

if(COUNTER[11])
DATA_10BIT_OUT_LIST[11] <={1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_12[6] ,
VIDEO_7BIT_IN_12[5] ,
VIDEO_7BIT_IN_12[4] ,
VIDEO_7BIT_IN_12[3] ,
VIDEO_7BIT_IN_12[2] ,
VIDEO_7BIT_IN_12[1] ,
VIDEO_7BIT_IN_12[0]
};

if(COUNTER[12])
DATA_10BIT_OUT_LIST[12] <={1'h0,
1'h1,
1'h0,
VIDEO_7BIT_IN_13[6] ,
VIDEO_7BIT_IN_13[5] ,
VIDEO_7BIT_IN_13[4] ,
VIDEO_7BIT_IN_13[3] ,
VIDEO_7BIT_IN_13[2] ,
VIDEO_7BIT_IN_13[1] ,
VIDEO_7BIT_IN_13[0]
};

if(COUNTER[13])
DATA_10BIT_OUT_LIST[13] <={1'h1,
1'h1,
1'h0,
VIDEO_7BIT_IN_14[6] ,
VIDEO_7BIT_IN_14[5] ,
VIDEO_7BIT_IN_14[4] ,
VIDEO_7BIT_IN_14[3] ,
VIDEO_7BIT_IN_14[2] ,
VIDEO_7BIT_IN_14[1] ,
VIDEO_7BIT_IN_14[0]
};

DATA_10BIT_OUT_BUF[0] <= DATA_10BIT_OUT_LIST[0] |
DATA_10BIT_OUT_LIST[1] |
DATA_10BIT_OUT_LIST[2] |
DATA_10BIT_OUT_LIST[3];

DATA_10BIT_OUT_BUF[1] <= DATA_10BIT_OUT_LIST[4] |
DATA_10BIT_OUT_LIST[5] |
DATA_10BIT_OUT_LIST[6] |
DATA_10BIT_OUT_LIST[7];

DATA_10BIT_OUT_BUF[2] <= DATA_10BIT_OUT_LIST[8] |
DATA_10BIT_OUT_LIST[9] |
DATA_10BIT_OUT_LIST[10] |
DATA_10BIT_OUT_LIST[11];

DATA_10BIT_OUT_BUF[3] <= DATA_10BIT_OUT_LIST[12] |
DATA_10BIT_OUT_LIST[13];

DATA_10BIT_OUT <= DATA_10BIT_OUT_BUF[0] |
DATA_10BIT_OUT_BUF[1] |
DATA_10BIT_OUT_BUF[2] |
DATA_10BIT_OUT_BUF[3];

只看该作者 · 2013-4-10 08:58

:lol

只看该作者 · 2013-4-10 16:02

本帖最后由 cxh_boy 于 2013-4-10 16:10 编辑

resxpl 发表于 2013-4-9 21:04
改进方法在前面已经给出来了. 基本就是分解逻辑. 利用延迟几个周期达到提高定时性能的目的.
前面只是简单改 ...

试了下,这样子没有之前效果好！可能主要是我的资源太少了,已经到90%了！你的分解逻辑的方法,受教了,很有用,谢过！
另外：
Slack                   From Node                                                                   To Node                                                                            Lanuch  Clock       LatchClock
-3.503  DATA_CONNECT ：DATA_CONNECT_MY|COUNTER[1] DATA_CONNECT：DATA_CONNECT_MY|DATA_10BIT_OUT[3]       SYSCLK                SYSCLK

这句话的意思是说： COUNTER[1]  到 DATA_10BIT_OUT[3] 的余量是-3.503ns吗？照常理说,内部reg 到reg应该很快才对, 怎么会这么大的延迟呢？感觉有点说不过去？