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verilog 中，过程赋值语句（always块中“＝”与“<=”）的左边不能用wire型，一般用reg型信号。但是如果这个always块表现的是一个组合逻辑的话，实际综合的结果，常常使得这些reg型信号被优化掉或展现为wire。
有点奇怪的矛盾。
比如：
module test(
input a,
input b,
input[1:0] f,
output c,
output e
); reg d; assign c = a & b;
assign e = d & a & b;
// Usage of asynchronous resets may negatively impact FPGA resources
// and timing. In general faster and smaller FPGA designs will
// result from not using asynchronous resets. Please refer to
// the Synthesis and Simulation Design Guide for more information.
// Always specify an else statement with a combinatorial if statement in
// order to avoid the inference of a latch
always @*
if (b) begin
d = f[0];
end
else d = a;
endmodule
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