如题，rd信号和addr信号一直不变，但是AD_DATA1 <= data_bus; //16'b1111111111000001;//这两句是可以执行的
module ADS8364 (data_bus_out,
clk_in,start_in,rst_in,start,rst,add,addr,data_bus,cs,rd,clk,Eoc,Byte,AD_DATA1,AD_DATA2,AD_DATA3,AD_DATA4,AD_DATA5,AD_DATA6,Ad_ready,EOC_OUT
,eoc_flag);
//定义输入输出管脚
input [15:0] data_bus; //ADS8364 16bit input
input Eoc; //ADS8364 EOC=0
input clk_in;
input start_in;
input rst_in;
output [15:0] data_bus_out;
output start;
output rst;
output add;
output [2:0] addr;
output cs;
output rd;
output clk;
output Byte;
output [15:0] AD_DATA1;
output [15:0] AD_DATA2;
output [15:0] AD_DATA3;
output [15:0] AD_DATA4;
output [15:0] AD_DATA5;
output [15:0] AD_DATA6;
output [7:0] Ad_ready;
output EOC_OUT;
output eoc_flag;
//定义数据类型
wire [15:0] data_bus_out;
reg start;
reg rst;
reg add;
reg [2:0] addr;
reg cs;
reg rd;
reg clk;
reg Byte;
reg [15:0] AD_DATA1;
reg [15:0] AD_DATA2;
reg [15:0] AD_DATA3;
reg [15:0] AD_DATA4;
reg [15:0] AD_DATA5;
reg [15:0] AD_DATA6;
reg [4:0] k;
reg [7:0] Ad_ready;
reg EOC_OUT;
reg eoc_flag;
reg [3:0] state;
reg clear_eoc_flag;
//reg [15:0] data_bus;
wire [15:0] data_bus;
wire Eoc;
wire clk_in;
wire start_in;
wire rst_in;
wire start_flag;
wire Ad_rdy;
parameter state0=4'b0000,
state1=4'b0001,
state2=4'b0010,
state3=4'b0011,
state4=4'b0100,
state5=4'b0101,
state6=4'b0110,
state7=4'b0111,
state8=4'b1000,
state9=4'b1001,
state10=4'b1010,
state11=4'b1011,
state12=4'b1100,
state13=4'b1101,
state14=4'b1110,
state15=4'b1111;
/*clk_pulse*/
always @(posedge clk_in)
begin
if(k>=20)
begin
clk <= ~clk; // 1.25MHz
k <= 0;
end
else k <= k+1;
end
assign data_bus_out = data_bus; //ADS8364 shujushuchu
/*reset_signal*/
always @(posedge clk_in or negedge rst_in or negedge start_in or negedge Eoc)
begin
rst <= rst_in;
start <= start_in;
EOC_OUT <= Eoc;
end
always @ (negedge Eoc or posedge clear_eoc_flag or negedge rst_in)
begin
if( !rst_in || clear_eoc_flag)
begin
eoc_flag <= 0;
end
else if(!Eoc)
eoc_flag <= 1;
end
always@(posedge clk_in or negedge rst_in or negedge Eoc)
begin
if(!rst_in)
begin
state <= state0;
end
else
begin
case(state)//----不断的将下一个状态赋给当前状态 --//
state0: //--初始化 reset
begin
add <= 0; //no second round
addr <= 3'b000;//A2,A1,A0-110 cycle model
cs <= 0; // always selected
rd <= 1;
//AD_DATA1 <=0;
Byte <= 0; //16bit data_bus
// start_cnt <= 0;
//Ad_ready <= 8'b11111111;
//rd_flag = 0;
clear_eoc_flag <= 0;
state <= state1;
end
state1: //wait for eoc
begin
if(eoc_flag) //!Eoc
begin
state <= state2;
end
end
state2: //choose A0
begin
clear_eoc_flag <= 1;
rd <= 0;
addr <= 3'b000;
state <= state3;
end
state3:
begin //A0数据输出
#10000
AD_DATA1 <= data_bus; //16'b1111111111000001;//
rd <= 1;
state <= state4;
end
state4: //choose A0
begin
#10000
clear_eoc_flag <= 1;
rd <= 0;
addr <= 3'b001;
state <= state5;
end
state5:
begin //A0数据输出
#10000
AD_DATA2 <= data_bus; //16'b1111111111000001;//
rd <= 1;
state <= state0;
end
default:
state=state0;
endcase
end
end
endmodule |
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