谁用altera，来试试下面的代码

只看该作者 · 2013-7-15 20:40

本帖最后由 drentsi 于 2013-7-15 20:42 编辑

使用xilinx的V7，xst报告的速度只有151M，不知altera是什么表现？
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sa_test is
port(
sys_clk :in std_logic;
din_a  :in std_logic_vector(0 to 31);
din_b  :in std_logic_vector(0 to 31);
din_c  :in std_logic_vector(0 to 31);
din_d  :in std_logic_vector(0 to 31);
dout_a : out std_logic_vector(0 to 31);
dout_b : out std_logic_vector(0 to 31);
dout_c : out std_logic_vector(0 to 31);
dout_d : out std_logic_vector(0 to 31)
);
end sa_test;
architecture Behavioral of sa_test is
function ROTL (x: std_logic_vector(0 to 31);n :integer) return std_logic_vector is
begin
return (x(n to 31)&x(0 to n-1));
end function  ;
signal b_step0:std_logic_vector(0 to 31);
signal c_step0:std_logic_vector(0 to 31);
signal d_step0:std_logic_vector(0 to 31);
signal a_step0:std_logic_vector(0 to 31);
signal b_step1:std_logic_vector(0 to 31);
signal c_step1:std_logic_vector(0 to 31);
signal d_step1:std_logic_vector(0 to 31);
signal a_step1:std_logic_vector(0 to 31);
signal b_d1:std_logic_vector(0 to 31);
signal c_d1:std_logic_vector(0 to 31);
signal d_d1:std_logic_vector(0 to 31);
signal a_d1:std_logic_vector(0 to 31);
signal r1_step0:std_logic_vector(0 to 31);
signal r2_step0:std_logic_vector(0 to 31);
signal r3_step0:std_logic_vector(0 to 31);
signal r4_step0:std_logic_vector(0 to 31);
signal r1_step1:std_logic_vector(0 to 31);
signal r2_step1:std_logic_vector(0 to 31);
signal r3_step1:std_logic_vector(0 to 31);
signal r4_step1:std_logic_vector(0 to 31);

begin
r1_step0<=ROTL(din_a+din_d,7);
b_step0<=r1_step0 xor din_b;

r2_step0<=ROTL(din_a+b_step0,9);
c_step0<=r2_step0 xor din_c;

r3_step0<=ROTL(b_step0+c_step0,13);
d_step0<=r3_step0 xor din_d;

r4_step0<=ROTL(c_step0+d_step0,18);
a_step0<=r4_step0 xor din_a;
process(sys_clk)
begin
if sys_clk'event and sys_clk='1' then
b_d1<=b_step0;
c_d1<=c_step0;
d_d1<=d_step0;
a_d1<=a_step0;
end if;
end process;

r1_step1<=ROTL(a_d1+d_d1,7);
b_step1<=r1_step1 xor b_d1;

r2_step1<=ROTL(a_d1+b_step1,9);
c_step1<=r2_step1 xor c_d1;

r3_step1<=ROTL(b_step1+c_step1,13);
d_step1<=r3_step1 xor d_d1;

r4_step1<=ROTL(c_step1+d_step1,18);
a_step1<=r4_step1 xor a_d1;

process(sys_clk)
begin
if sys_clk'event and sys_clk='1' then
dout_b<=b_step1;
dout_c<=c_step1;
dout_d<=d_step1;
dout_a<=a_step1;
end if;
end process;
end Behavioral;