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请大狭帮看下程序--怎么没有输出????

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www888www|  楼主 | 2007-4-15 18:08 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ram0 is 
port(   clk    :in std_logic;
        reset  :in std_logic;  
        q1_1   :out std_logic_vector(7 downto 0); 
        q2_2   :out std_logic_vector(7 downto 0);    
        data1_1:out std_logic_vector(7 downto 0);
        data2_2:out std_logic_vector(7 downto 0);
   wraddress1_1:out std_logic_vector(3 downto 0);
        datain :in std_logic_vector(7 downto 0);
        dataout:out std_logic_vector(7 downto 0)
);
end ram0;
--********************************************************
architecture behave of ram0 is
signal data1  : std_logic_vector(7 downto 0);
signal data2  : std_logic_vector(7 downto 0);

signal    q1  : std_logic_vector(7 downto 0);
signal    q2  : std_logic_vector(7 downto 0);

signal wren1  : std_logic;
signal wraddress1  : std_logic_vector(3 downto 0);
signal rden1  : std_logic;
signal rdaddress1  : std_logic_vector(3 downto 0);
signal wren2  : std_logic;
signal wraddress2  : std_logic_vector(3 downto 0);
signal rden2  : std_logic;
signal rdaddress2  : std_logic_vector(3 downto 0);




component ram1
    PORT
    (
        data        : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        wren        : IN STD_LOGIC;
        wraddress       : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        rdaddress    : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        rden        : IN STD_LOGIC;
        clock        : IN STD_LOGIC;
        q        : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    );
end component;
component ram2
    PORT
    (
        data        : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        wren        : IN STD_LOGIC;
        wraddress    : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        rdaddress    : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        rden        : IN STD_LOGIC;
        clock        : IN STD_LOGIC;
        q        : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    );
end component;
--*********************************************************
begin
q1_1<=q1;
q2_2<=q2;
data1_1<=data1;
data2_2<=data2;
wraddress1_1<= wraddress1;

ram1_inst : ram1 PORT MAP 
(        data     =>data1,
        wren     => wren1,
        wraddress=> wraddress1,
        rdaddress=> rdaddress1,
        rden     => rden1,
        clock     => clk,
        q     => q1
    );
ram2_inst : ram2 PORT MAP (
        data     => data2,
        wren     => wren2,
        wraddress=> wraddress2,
        rdaddress=> rdaddress2,
        rden     => rden2,
        clock     => clk,
        q     => q2
    );
    
u1:process(reset,clk)
begin
   if(reset='0')then
   wraddress1<="0000";
   elsif(clk'event and clk='1')then
         wren1<='1';
         wraddress1<=wraddress1+1;
      if wraddress1<="0000" then
            data1<=datain;
         elsif wraddress1="0001" then 
               data1<=datain;
         elsif wraddress1="0010" then 
               data1<=datain;
         elsif wraddress1="0011" then 
               data1<=datain;
         elsif wraddress1="0100" then 
               data1<=datain;
         elsif wraddress1="0101" then 
               data1<=datain;
         elsif wraddress1="0110" then 
               data1<=datain;
         elsif wraddress1="0111" then 
               data1<=datain;
         elsif wraddress1="1000" then 
               data1<=datain;
         elsif wraddress1="1001" then 
               data1<=datain;
         elsif wraddress1="1010" then 
               data1<=datain;
         elsif wraddress1="1011" then 
               data1<=datain;
         elsif wraddress1="1100" then 
               data1<=datain;  
         elsif wraddress1="1101" then 
               data1<=datain; 
         elsif wraddress1="1110" then 
               data1<=datain; 
         elsif wraddress1="1111" then 
               data1<=datain; 
         end if;
   end if;      
end process; 
--******************************************************* 
u2:process(reset,clk) 
    begin
   if (reset<='0') then
      wraddress2<="0000";
   elsif (clk'event and clk='1') then
         wren2<='1';    
         wraddress2<=wraddress2+1;
         if wraddress2="0000" then
            data2<=q1;
         elsif wraddress2="0001" then 
               data2<=q1;
         elsif wraddress2="0010" then 
               data2<=q1;
         elsif wraddress2="0011" then 
               data2<=q1;
         elsif wraddress2="0100" then 
               data2<=q1;
         elsif wraddress2="0101" then 
               data2<=q1;
         elsif wraddress2="0110" then 
               data2<=q1;
         elsif wraddress2="0111" then 
               data2<=q1;
         elsif wraddress2="1000" then 
               data2<=q1;
         elsif wraddress2="1001" then 
               data2<=q1;
         elsif wraddress2="1010" then 
               data2<=q1;
         elsif wraddress2="1011" then 
               data2<=q1;
         elsif wraddress2="1100" then 
               data2<=q1;  
         elsif wraddress2="1101" then 
               data2<=q1; 
         elsif wraddress2="1110" then 
               data2<=q1; 
         elsif wraddress2="1111" then 
               data2<=q1; 
         end if;
    end if;      
end process;  
--********************************************************
u3:process(clk,reset)
   begin
   if reset<='0' then
      rdaddress2<="0000";
   elsif (clk'event and clk='1') then
          rden2<='1';
         rdaddress2<=rdaddress2+1; 
         if rdaddress2="0000" then
            dataout<=q2;
         elsif rdaddress2="0001" then 
               dataout<=q2;
         elsif rdaddress2="0010" then 
               dataout<=q2;
         elsif rdaddress2="0011" then 
               dataout<=q2;
         elsif rdaddress2="0100" then 
               dataout<=q2;
         elsif rdaddress2="0101" then 
               dataout<=q2;
         elsif rdaddress2="0110" then 
               dataout<=q2;
         elsif rdaddress2="0111" then 
               dataout<=q2;
         elsif rdaddress2="1000" then 
               dataout<=q2;
         elsif rdaddress2="1001" then 
               dataout<=q2;
         elsif rdaddress2="1010" then 
               dataout<=q2;
         elsif rdaddress2="1011" then 
               dataout<=q2;
         elsif rdaddress2="1100" then 
               dataout<=q2;
         elsif rdaddress2="1101" then 
               dataout<=q2;
         elsif rdaddress2="1110" then 
               dataout<=q2;
         elsif rdaddress2="1111" then 
               dataout<=q2;
         end if;
     end if;

end process;  
end behave;







      

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