求助！！！！verilog实现解码

只看该作者 · 2013-7-31 16:44

module sender_module(clk,rstn,load,code);
input clk;
input rstn;
output load;
output [3:0]code;
reg rload;
reg [3:0]code;
reg[1:0]count;
always@(posedge clk or negedge rstn)
if(!rstn)
count<=0;
else if(count==3)
count<=0;
else
count<=count+1'b1;
always@(posedge clk or negedge rstn)
if(!rstn)
rload<=1'b0;
else if(count==0)
begin
   rload<=1'b1;
end
else if(count>=1 && count<=3)
rload<=1'b0;
assign load=rload;
reg [3:0]state;
always@(posedge clk or negedge rstn)
if(!rstn)
state<=4'b0001;
else if(load==1'b1)
case(state)
4'b0001: begin code<=4'b1111;state<=4'b0010; end
4'b0010: begin code<=4'b0110;state<=4'b0100; end
4'b0100: begin code<=4'b0101;state<=4'b1000; end
4'b1000: begin code<=4'b0100;state<=4'b0000; end
4'b0000: begin code<=4'bxxxx;end
default:  state=4'b0001;
endcase
else if(load==1'b0)
code<=4'bxxxx;
endmodule
`timescale 1 ps/ 1 ps
module sender_module_vlg_tst();
// constants
// general purpose registers
//reg eachvec;
// test vector input registers
reg clk;
reg rstn;
reg rload;
// wires
wire load;
wire [3:0]  code;
assign #1 load=rload;

// assign statements (if any)
sender_module i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.code(code),
.load(load),
.rstn(rstn)
);
initial
begin
// code that executes only once
// insert code here --> begin

// --> end
clk=0;
rstn=1;
#7 rstn=0;
#5 rstn=1;
$display("Running testbench");
end
always #5 clk=~clk;
// optional sensitivity list
// @(event1 or event2 or .... eventn)
// code executes for every event on sensitivity list
// insert code here --> begin

//@eachvec;
// --> end
endmodule
求帮忙看看，为什么没有输出，不胜感激，这个问题已经卡了快一个礼拜了，非常感谢！