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library IEEE;<br />use IEEE.std_logic_1164.all;<br /><br />entity adder16_2 is<br /> generic(N : integer := 16);<br /> port (a : in std_logic_vector(N downto 1);<br /> b : in std_logic_vector(N downto 1);<br /> cin : in std_logic;<br /> sum : out std_logic_vector(N downto 1);<br />-- cout : inout std_logic;<br /> carry_1 : inout std_logic);<br />end adder16_2;<br />architecture structural of adder16_2 is<br /> component adder<br /> port (a : in std_logic;<br /> b : in std_logic;<br /> cin : in std_logic;<br /> sum : out std_logic;<br />-- cout : inout std_logic;<br /> carry_1 : inout std_logic);<br /> end component;<br /> signal tempcarry_1 : std_logic_vector(0 to N);<br /> begin<br /> tempcarry_1(0) <= cin;<br />-- cout <= tempcarry_1(N);<br /> gen: for I in 1 to N generate<br /> add: adder port map<br /> ( a => a(I),<br /> b => b(I),<br /> cin => tempcarry_1(I - 1),<br /> sum => sum(I),<br /> carry_1 => tempcarry_1(4)<br />-- cout => carry_1<br /> );<br /> end generate;<br />end structural;<br />architecture behavioral of adder16_2 is<br />begin<br />p1: process(a, b, cin)<br /> variable tempsum_1 : std_logic_vector(4 downto 1);<br /> variable tempcarry_1 : std_logic;<br /> begin<br /> tempcarry_1 := cin;<br /> for i in 1 to 4 loop<br /> tempsum_1(i) := (a(i) xor b(i)) xor tempcarry_1;<br /> tempcarry_1 := (a(i) and b(i)) or (tempcarry_1 and (a(i) or b(i)));<br /> end loop;<br /> carry_1 <= tempcarry_1;<br />-- cout <= carry_1;<br /> end process p1;<br />p2: process(a, b, carry_1)<br /> variable tempsum_2 : std_logic_vector(8 downto 5);<br /> variable tempcarry_2 : std_logic;<br /> variable tempsum_2_1 : std_logic_vector(8 downto 5);<br /> variable tempcarry_2_1 : std_logic;<br /> variable tempsum_2_2 : std_logic_vector(8 downto 5);<br /> variable tempcarry_2_2 : std_logic;<br /> begin<br /> for i in 5 to 8 loop<br /> tempsum_2_1(i) := (a(i) xor b(i));<br /> tempcarry_2_1 := (a(i) and b(i));<br /> tempsum_2_2(i) := (not (a(i) xor b(i)));<br /> tempcarry_2_2 := (a(i) or b(i));<br /> end loop;<br /> case carry_1 is<br /> when 0 =><br /> tempsum_2 := tempcarry_2_1;<br /> tempcarry_2 := tempcarry_2_1;<br /> when 1 =><br /> tempsum_2 := tempcarry_2_2;<br /> tempcarry_2 := tempcarry_2_2;<br /> when others => null;<br /> end case;<br /> end process p2;<br />p3: process(a, b, tempcarry_2)<br /> variable tempsum_3 : std_logic_vector(12 downto 9);<br /> variable tempcarry_3 : std_logic;<br /> variable tempsum_3_1 : std_logic_vector(12 downto 9);<br /> variable tempcarry_3_1 : std_logic;<br /> variable tempsum_3_2 : std_logic_vector(12 downto 9);<br /> variable tempcarry_3_2 : std_logic;<br /> begin<br /> for i in 9 to 12 loop<br /> tempsum_3_1(i) := (a(i) xor b(i));<br /> tempcarry_3_1 := (a(i) and b(i));<br /> tempsum_3_2(i) := (not (a(i) xor b(i)));<br /> tempcarry_3_2 := (a(i) or b(i));<br /> end loop;<br /> case tempcarry_2 is<br /> when 0 =><br /> tempsum_3 := tempcarry_3_1;<br /> tempcarry_3 := tempcarry_3_1;<br /> when 1 =><br /> tempsum_3 := tempcarry_3_2;<br /> tempcarry_3 := tempcarry_3_2;<br /> when others => null;<br /> end case;<br /> end process p3;<br />p4: process(a, b, tempcarry_3)<br /> variable tempsum_4 : std_logic_vector(16 downto 13);<br /> variable tempcarry_4 : std_logic;<br /> variable tempsum_4_1 : std_logic_vector(16 downto 13);<br /> variable tempcarry_4_1 : std_logic;<br /> variable tempsum_4_2 : std_logic_vector(16 downto 13);<br /> variable tempcarry_4_2 : std_logic;<br /> begin<br /> for i in 13 to 16 loop<br /> tempsum_4_1(i) := (a(i) xor b(i));<br /> tempcarry_4_1 := (a(i) and b(i));<br /> tempsum_4_2(i) := (not (a(i) xor b(i)));<br /> tempcarry_4_2 := (a(i) or b(i));<br /> end loop;<br /> case tempcarry_3 is<br /> when 0 =><br /> tempsum_4 := tempcarry_4_1;<br /> tempcarry_4 := tempcarry_4_1;<br /> when 1 =><br /> tempsum_4 := tempcarry_4_2;<br /> tempcarry_4 := tempcarry_4_2;<br /> when others => null;<br /> end case;<br /> end process p4;<br /> sum <= tempsum_4&tempsum_3&tempsum_2&tempsum_1;<br /> cout <= tempcarry_4;<br />end behavioral;<br /><br /><br /><br />改了一下<br /><br />错误<br /><br />Error (10517): VHDL type mismatch error at adder16_2.vhd(66): std_logic type does not match integer literal<br />Error (10517): VHDL type mismatch error at adder16_2.vhd(69): std_logic type does not match integer literal<br />Error (10523): Ignored construct behavioral at adder16_2.vhd(37) due to previous errors<br /><br />那个carry_1是不是要声明成ventor啊?<br />case后边的变量用什么类型可以呢? |
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