library IEEE;
use IEEE.std_logic_1164.all;
entity adder16_2 is
generic(N : integer := 16);
port (a : in std_logic_vector(N downto 1);
b : in std_logic_vector(N downto 1);
cin : in std_logic;
sum : out std_logic_vector(N downto 1);
-- cout : inout std_logic;
carry_1 : inout std_logic);
end adder16_2;
architecture structural of adder16_2 is
component adder
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
-- cout : inout std_logic;
carry_1 : inout std_logic);
end component;
signal tempcarry_1 : std_logic_vector(0 to N);
begin
tempcarry_1(0) <= cin;
-- cout <= tempcarry_1(N);
gen: for I in 1 to N generate
add: adder port map
( a => a(I),
b => b(I),
cin => tempcarry_1(I - 1),
sum => sum(I),
carry_1 => tempcarry_1(4)
-- cout => carry_1
);
end generate;
end structural;
architecture behavioral of adder16_2 is
begin
p1: process(a, b, cin)
variable tempsum_1 : std_logic_vector(4 downto 1);
variable tempcarry_1 : std_logic;
begin
tempcarry_1 := cin;
for i in 1 to 4 loop
tempsum_1(i) := (a(i) xor b(i)) xor tempcarry_1;
tempcarry_1 := (a(i) and b(i)) or (tempcarry_1 and (a(i) or b(i)));
end loop;
carry_1 <= tempcarry_1;
-- cout <= carry_1;
end process p1;
p2: process(a, b, carry_1)
variable tempsum_2 : std_logic_vector(8 downto 5);
variable tempcarry_2 : std_logic;
variable tempsum_2_1 : std_logic_vector(8 downto 5);
variable tempcarry_2_1 : std_logic;
variable tempsum_2_2 : std_logic_vector(8 downto 5);
variable tempcarry_2_2 : std_logic;
begin
for i in 5 to 8 loop
tempsum_2_1(i) := (a(i) xor b(i));
tempcarry_2_1 := (a(i) and b(i));
tempsum_2_2(i) := (not (a(i) xor b(i)));
tempcarry_2_2 := (a(i) or b(i));
end loop;
case carry_1 is
when 0 =>
tempsum_2 := tempcarry_2_1;
tempcarry_2 := tempcarry_2_1;
when 1 =>
tempsum_2 := tempcarry_2_2;
tempcarry_2 := tempcarry_2_2;
when others => null;
end case;
end process p2;
p3: process(a, b, tempcarry_2)
variable tempsum_3 : std_logic_vector(12 downto 9);
variable tempcarry_3 : std_logic;
variable tempsum_3_1 : std_logic_vector(12 downto 9);
variable tempcarry_3_1 : std_logic;
variable tempsum_3_2 : std_logic_vector(12 downto 9);
variable tempcarry_3_2 : std_logic;
begin
for i in 9 to 12 loop
tempsum_3_1(i) := (a(i) xor b(i));
tempcarry_3_1 := (a(i) and b(i));
tempsum_3_2(i) := (not (a(i) xor b(i)));
tempcarry_3_2 := (a(i) or b(i));
end loop;
case tempcarry_2 is
when 0 =>
tempsum_3 := tempcarry_3_1;
tempcarry_3 := tempcarry_3_1;
when 1 =>
tempsum_3 := tempcarry_3_2;
tempcarry_3 := tempcarry_3_2;
when others => null;
end case;
end process p3;
p4: process(a, b, tempcarry_3)
variable tempsum_4 : std_logic_vector(16 downto 13);
variable tempcarry_4 : std_logic;
variable tempsum_4_1 : std_logic_vector(16 downto 13);
variable tempcarry_4_1 : std_logic;
variable tempsum_4_2 : std_logic_vector(16 downto 13);
variable tempcarry_4_2 : std_logic;
begin
for i in 13 to 16 loop
tempsum_4_1(i) := (a(i) xor b(i));
tempcarry_4_1 := (a(i) and b(i));
tempsum_4_2(i) := (not (a(i) xor b(i)));
tempcarry_4_2 := (a(i) or b(i));
end loop;
case tempcarry_3 is
when 0 =>
tempsum_4 := tempcarry_4_1;
tempcarry_4 := tempcarry_4_1;
when 1 =>
tempsum_4 := tempcarry_4_2;
tempcarry_4 := tempcarry_4_2;
when others => null;
end case;
end process p4;
sum <= tempsum_4&tempsum_3&tempsum_2&tempsum_1;
cout <= tempcarry_4;
end behavioral;
改了一下
错误
Error (10517): VHDL type mismatch error at adder16_2.vhd(66): std_logic type does not match integer literal
Error (10517): VHDL type mismatch error at adder16_2.vhd(69): std_logic type does not match integer literal
Error (10523): Ignored construct behavioral at adder16_2.vhd(37) due to previous errors
那个carry_1是不是要声明成ventor啊?
case后边的变量用什么类型可以呢? |
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