根据输入确定输出值
library ieee;
use ieee.std_logic_1164.all;
entity mux41 is
port(s4,s3,s2,s1: in std_logic;
z4,z3,z2,z1: out std_logic);
end mux41;
architecture art of mux41 is
begin
process(s4, s3, s2, s1)
variable sel: integer range 0to15;
begin
sel:=0;
if s1=‘1’ then sel:=sel+1; end if;
if s2=‘1’ then sel:=sel+2; end if;
if s3=‘1’ then sel:=sel+4; end if;
if s4=‘1’ then sel:=sel+8; end if;
z1<=‘0’; z2<=‘0’; z3<=‘0’; z4<=‘0’;
case sel is
when 0 =>z1<=‘1’;
when 1|3 =>z2<=‘1’;
when 4 to 7|2 =>z3<=‘1’;
when others =>z4<=‘1’;
end case;
end process;
end art;
按要求应该是根据四位输入码来确定四位输入中哪一位输出为1，但这程序貌似不是这样的，还有那case语句中1，3，4，7，2.。。。。是怎么确定的哦？？
谢谢了~~~ |
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