Error (10482): VHDL error at bell.vhd(21): object "clk_in" is used but not declared
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity bell is
port(clk_in:in std_logic;
reset:in std_logic;
fengming:out std_logic);
end bell;
architecture behave of fenpin is
signal clk_temp:std_logic;--蜂鸣器驱动时钟信号
signal pre_div:std_logic_vector(15 downto 0);--装预置分频数
component fenpin is
port(clk:in std_logic;
clk_out:out std_logic);
end component;
begin
gen_10M:fenpin port map (clk=>clk_in,clk_out=>clk_temp);
process(clk_temp)
variable cnt1:std_logic_vector(15 downto 0):=X"0000";--分频计数器
variable cnt2:integer range 0 to 7000:=0; --蜂鸣时间
begin
fengming<=clk_temp; --蜂鸣输出
if reset='0'then --复位时
cnt1:='0';
cnt2:='0';
pre_div<="12a2";
if rising_edge(clk_temp) then --时钟上升沿到来时
if cnt1=12a2 then
cnt1:=x"0000";
clk_temp<=not clk_temp;
cnt2:=cnt2+1;
if cnt2=1000 then --响500个时钟
pre_div<=109b;
elsif cnt2=2000 then
pre_div<=ecb;
elsif cnt2=3000 then
pre_div<=dfd;
elsif cnt2=4000 then
pre_div<=c74;
elsif cnt2=5000 then
pre_div<=b18;
elsif cnt2=6000 then
pre_div<=9e2;
elsif cnt2=7000 then
pre_div<=12a2;
end if;
else
cnt1:=cnt1+1;
end if;
end if;
end if;
end process;
end behave; |
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