VHDL仿真testbench书写问题

只看该作者 · 2013-11-13 13:51

1.本程序是串口接收程序，收到的数据是乱的，我想仿真下。程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fasong is
port(
clkin  :in std_logic;
resetin:in std_logic;
rx    :in std_logic;
led :out std_logic_vector(2 downto 0)
   );
end fasong;
architecture behave of fasong is
signal clk_temp:std_logic;
signal led_temp:std_logic_vector(7 downto 0);
component uart_r is
  port(clk_r  :in std_logic;
reset_r:in std_logic;
rx_in  :in std_logic;  --串口数据输入
rx_out :out std_logic_vector(7 downto 0);--串口输入输出
ready:out std_logic);--接收一帧数据结束标志信号
end component;

component fenpin is
port(clk:in std_logic;
reset_t:in std_logic;
clk_out:out std_logic);
end component;
begin
U1:fenpin port map(clk=>clkin,reset_t=>resetin,clk_out=>clk_temp);
U2:uart_r port map(clk_r=>clk_temp,reset_r=>resetin,rx_in=>rx,rx_out=>led_temp);
process(resetin,clkin)
begin
  if resetin='0' then
led<="111";
  else
if clkin'event and clkin='1' then
case led_temp is
   when x"00"=>led<="000";
   when x"01"=>led<="001";
   when x"02"=>led<="010";
   when x"03"=>led<="011";
   when x"04"=>led<="111";
   when others=>led<="000";
end case;
end if;
  end if;
end process;
end behave;

2.testbench如下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fasong is
port(
clkin  :in std_logic;
resetin:in std_logic;
rx    :in std_logic;
led :out std_logic_vector(2 downto 0)
   );
end fasong;
architecture behave of fasong is
signal clk_temp:std_logic;
signal led_temp:std_logic_vector(7 downto 0);
component uart_r is
  port(clk_r  :in std_logic;
reset_r:in std_logic;
rx_in  :in std_logic;  --´®¿ÚÊý¾ÝÊäÈë
rx_out :out std_logic_vector(7 downto 0);--´®¿ÚÊäÈëÊä³ö
ready:out std_logic);--½ÓÊÕÒ»Ö¡Êý¾Ý½áÊø±êÖ¾ÐÅºÅ
end component;

component fenpin is
port(clk:in std_logic;
reset_t:in std_logic;
clk_out:out std_logic);
end component;
begin
U1:fenpin port map(clk=>clkin,reset_t=>resetin,clk_out=>clk_temp);
U2:uart_r port map(clk_r=>clk_temp,reset_r=>resetin,rx_in=>rx,rx_out=>led_temp);
process(resetin,clkin)
begin
  if resetin='0' then
led<="111";
  else
if clkin'event and clkin='1' then
case led_temp is
   when x"00"=>led<="000";
   when x"01"=>led<="001";
   when x"02"=>led<="010";
   when x"03"=>led<="011";
   when x"04"=>led<="111";
   when others=>led<="000";
end case;
end if;
  end if;
end process;
end behave;
testbench我觉得有问题，但是不知道如何写是好？