本帖最后由 niuyuanhai 于 2014-4-16 15:32 编辑
感谢各位帮助,耽误大家时间了,情况是这样的:
DSP28335通过MCBSP的clock stop模式(SPI协议)向AD9834写频率字,正确的时序图应该是这样的:
但是我的时序测出来是这样子的:
第二个图:
第一条:帧同步信号
第二条:clk
第三条:data
我配置的MCBSP代码如下:
McbspbRegs.SPCR2.bit.XRST=0; McbspbRegs.SPCR1.bit.RRST=0;
McbspbRegs.SPCR2.bit.GRST=0;
McbspbRegs.SPCR1.bit.CLKSTP=11; //enable or diable the Clock Stop Mood McbspbRegs.PCR.bit.CLKXP=1; //set the transmit clock polarity
McbspbRegs.PCR.bit.CLKRP=1;
McbspbRegs.PCR.bit.CLKXM=1;
McbspbRegs.PCR.bit.SCLKME=0;
McbspbRegs.SRGR2.bit.CLKSM=1;
McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1)
McbspbRegs.PCR.bit.FSXM=1; //Transmit frame-synchronization mode
McbspbRegs.SRGR2.bit.FSGM=0; //Sample rate generator transmit frame-synchronization mode
McbspbRegs.PCR.bit.FSXP=1; //Set the transmit frame-synchronization polarity
McbspbRegs.XCR2.bit.XDATDLY=01; //Set the Transmit Data Delay
McbspbRegs.RCR2.bit.RDATDLY=01;
McbspbRegs.XCR2.bit.XPHASE=0; //Choose one or two Phases for the Transmit Frame
McbspbRegs.RCR2.bit.RPHASE=0;
McbspbRegs.XCR1.bit.XFRLEN1=0;
McbspbRegs.RCR1.bit.RFRLEN1=0;
McbspbRegs.XCR1.bit.XWDLEN1=2;
McbspbRegs.RCR1.bit.RWDLEN1=2;
delay_loop();
McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
clkg_delay_loop(); // Wait at least 2 CLKG cycles
McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
|