vectros.asm程序设置如下：
;
; Copyright 2003 by Texas Instruments Incorporated.
; All rights reserved. Property of Texas Instruments Incorporated.
; Restricted rights to use, duplicate or disclose this code are
; granted through contract.
;
;
; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
;
; ======== vectors.asm ========
; Plug in the entry point at RESET in the interrupt vector table
;
;
; ======== unused ========
; plug inifinite loop -- with nested branches to
; disable interrupts -- for all undefined vectors
;
unused .macro id
.global unused:id:
unused:id:
b unused:id: ; nested branches to block interrupts
nop 4
b unused:id:
nop
nop
nop
nop
nop
.endm
.sect ".vectors"
.ref _c_int00 ; C entry point
.ref _Timerint0_isr ;
.align 32*8*4 ; must be aligned on 256 word boundary
.def RESET
RESET: ; reset vector
mvkl _c_int00,b0 ; load destination function address to b0
mvkh _c_int00,b0
b b0 ; start branch to destination function
mvc PCE1,b0 ; address of interrupt vectors
mvc b0,ISTP ; set table to point here
nop 3 ; fill delay slot
nop
nop
;
; plug unused interrupts with infinite loops to
; catch stray interrupts
;
NMI: b irp
nop
nop
nop
nop
nop
nop
nop
unused 2
unused 3
INT4:
stw b0,*--b15
mvkl _Timerint0_isr,b0
mvkh _Timerint0_isr,b0
b b0
ldw *b15++,b0
nop 3
nop
nop
unused 5
unused 6
unused 7
unused 8
unused 9
unused 10
unused 11
unused 12
unused 13
unused 14
unused 15
interruptSet程序：
#include "global.h"
void InterrptInit()
{
//INTMUX2 =(INTMUX2&0xFFF0FFFF)|(4<<16);//T64P0_TINT12
CSR = 0x0101;//global
ISTP =0;
ICR = INT4_SET;
IER |= INT4_SET;
}
int timercnt=0;
interrupt void Timerint0_isr(void)
{
int intFlag;
intFlag = TIMER0->INTCTLSTAT;
// SETBIT(TIMER2->INTCTLSTAT, intFlag); //clear ISR
TIMER0->INTCTLSTAT = intFlag;
timercnt++;
}
timer0设置程序：
#include "global.h"
void Timer0Init(void)
{
/*Clear 0*/
TIMER0->TCR = 0;
/*PLUSEN=1:New timer features are available.*/
/*Note:if you want to use reload mode or compare interrupt, you must set this bit.*/
TIMER0->TGCR |= 0x10;
/*TIMMODE=1:The timer is in dual 32-bit timer unchained mode. */
TIMER0->TGCR |= TIMMODE_32BIT_UNCHAINED;
/*TIM12RS=1:Timer 1:2 is not in reset.*/
TIMER0->TGCR |= 0x1;
/*set Timer 1:2 PRD*/
TIMER0->PRD12 =PRD;//ENA_TXSLOT_INT;
/*Set a initial counter value in register TIM12*/
TIMER0->TIM12 = 0;
/*Reload Period Value*/
TIMER0->REL12 = PRD;
/*PRDINTEN12=1:Enable interrupt.*/
TIMER0->INTCTLSTAT |= PRDINTEN12_ENABLE;
TIMER0->TCR |=ENAMODE12_CONT_RELOAD;
#if 0
/*TIM34RS=1:Timer 3:4 is not in reset.*/
TIMER0->TGCR |= 0x2;
/*Set a initial counter value in register TIM34*/
TIMER0->TIM34 = 0;
/*set Timer3:4 PRD*/
TIMER0->PRD34 = PRD;
/*Reload Period Value*/
TIMER0->REL34 = PRD;
/*PRDINTEN34=1:Enable interrupt.*/
TIMER0->INTCTLSTAT |= PRDINTEN34_ENABLE;
//compare register value
TIMER0->CMP1 = PRD - T1; //RFCtrlInterrupt
TIMER0->CMP2 = PRD - T1-T3; //BBPReadyINT;
//-- for ramp debug
TIMER0->CMP3 = PRD- DELAY_TR -GUARD_BIT_TIME;
TIMER0->CMP4 = PRD- DELAY_TR + DELAY_TXSLOT-TIMER_FREQ;
TIMER0->INTCTLSTAT |= PRDINTEN12_ENABLE;
TIMER0->TCR = ENAMODE34_CONT_RELOAD;
TIMER0->TIM12 = 0;
TIMER2->TCR |= ENAMODE34_CONT_RELOAD;//0xC0:continuously with period reload,0x80:continuously TIMER2->TCR |= 0x800000;
#endif //0x40:one time
}
global.h:
extern cregister volatile unsigned int AMR;
/* Address Mode Register
*/
extern cregister volatile unsigned int CSR;
/* Control Status Register
*/
extern cregister volatile unsigned int IFR;
/* Interrupt Flag Register
*/
extern cregister volatile unsigned int ISR;
/* Interrupt Set Register
*/
extern cregister volatile unsigned int ICR;
/* Interrupt Clear Register
*/
extern cregister volatile unsigned int IER;
/* Interrupt Enable Register
*/
extern cregister volatile unsigned int ISTP;
/* Interrupt Service Tbl Ptr
*/
extern cregister volatile unsigned int IRP;
/* Interrupt Return Pointer
*/
extern cregister volatile unsigned int NRP;
/* Non-maskable Int Return Ptr*/
extern cregister volatile unsigned int IN;
/* General Purpose Input Reg
*/
extern cregister volatile unsigned int OUT;
/* General Purpose Output Reg */
/*
定义中断选择寄存器
*/
/*
定义定时器
1
寄存器
*/
#define uint32_t unsigned int
typedef struct
{
volatile uint32_t REV ;
volatile uint32_t EMUMGT ;
volatile uint32_t GPINTGPEN ;
volatile uint32_t GPDATGPDIR ;
volatile uint32_t TIM12 ;
volatile uint32_t TIM34 ;
volatile uint32_t PRD12 ;
volatile uint32_t PRD34 ;
volatile uint32_t TCR ;
volatile uint32_t TGCR ;
volatile uint32_t WDTCR ;
volatile uint32_t Reserved0 ;
volatile uint32_t Reserved1 ;
volatile uint32_t REL12 ;
volatile uint32_t REL34 ;
volatile uint32_t CAP12 ;
volatile uint32_t CAP34 ;
volatile uint32_t INTCTLSTAT ;
volatile uint32_t Reserved[6] ;
volatile uint32_t CMP0;
volatile uint32_t CMP1;
volatile uint32_t CMP2;
volatile uint32_t CMP3;
volatile uint32_t CMP4;
volatile uint32_t CMP5;
volatile uint32_t CMP6;
volatile uint32_t CMP7;
}TIMER_REGISTER_t;
#define TIMER0_REG_BASE 0x01C20000 //Timer1 control register
#define INTMUX2_ADDR 0x01800108
#define INTMUX2 (*((volatile int *)INTMUX2_ADDR))
#define TIMER0 ((volatile TIMER_REGISTER_t *)TIMER0_REG_BASE)
#define TIMMODE_32BIT_UNCHAINED (1<<2) // bit 2
#define PRD (1000000)//
#define ENAMODE12_CONT_RELOAD (3<<6) // bit 6,7
#define PRDINTEN12_ENABLE (1<<0) // bit 0
#define INT4_SET (1<<4)
#define INT5_SET (1<<5)
#define INT6_SET (1<<6)
#define INT7_SET (1<<7)
#define INT8_SET (1<<8)
#define INT9_SET (1<<9)
#define INT10_SET (1<<10)
#define INT11_SET (1<<11)
#define INT12_SET (1<<12)
#define INT13_SET (1<<13)
#define INT14_SET (1<<14)
#define INT15_SET (1<<15)
void InterrptInit() ;
void Timer0Init(void);
main():
#include "global.h"
#include <stdio.h>
#include <stdlib.h>
int i1,i2;
void main()
{
int n;
InterrptInit();
Timer0Init();
while(1)
{
i1=TIMER0->TIM12;
i2=TIMER0->PRD12;
n++;
//printf("i=%d\r\n",i);
};
}
出现的问题：
TMS320C64X+_0: Warning: CPU:Interrupt No. 4 dropped, an earlier interrupt is pending to be taken
就是中断进不去，到不了vectors.asm的中断，请高手指点
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