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RomBaseAddr EQU &0<br />RomEndAddr EQU &20<br />RamBaseAddr EQU &100<br />RamEndAddr EQU &200 <br /> <br /> AREA text, CODE, READONLY <br /><br />SFR_BASE EQU 0x3ff ;0x3ff0000<br />SRAM_BASE EQU 0x3f8 ;0x3f80000<br /> <br /> ;EXPORT InitMemory<br />InitMemory<br /> ldr r0, =SYSCFG<br /> ldr r1, =SDRAM_ITF :OR: SFR_BASE<<16 :OR: SRAM_BASE<<16 :OR: CACHE_ALL :OR: CACHE_EN <br /> str r1, [r0]<br /> <br /> ldr r0, =CLKCON<br /> ldr r1, =0<br /> str r1, [r0]<br /> <br /> ldr r0, =EXTACON0<br /> ldr r1, =0x0fff0fff<br /> str r1, [r0]<br /> ldr r0, =EXTACON1<br /> ldr r1, =0x0fff0fff <br /> str r1, [r0]<br /> <br /> ldr r0, =EXTDBWTH<br /> ldr r1, =0xffff556<br /> str r1, [r0]<br /> <br /> adr r0, MemCfgPara<br /> ldmia r0, {r1-r11}<br /> ldr r0, =ROMCON0 <br /> stmia r0, {r1-r11}<br /> <br /> mov pc, r14<br /> <br />MemCfgPara<br /> DCD RomBaseAddr<<16 :OR RomEndAddr<<16 :OR: &60 ;&10840060<br /> DCD &10842060<br /> DCD &10842060<br /> DCD &10842060<br /> DCD &10842060<br /> DCD &10842060<br /> DCD RamBaseAddr<<16 :OR: RamEndAddr<<16 :OR: &398 ;&10000398<br /> DCD &10040398<br /> DCD &10040398<br /> DCD &10040398<br /> DCD &ce2983fd <br /> <br /> EXPORT RemapMemory<br />RemapMemory<br /> adr r0, RemapMemPara<br /> ldmia r0, {r1-r11}<br /> ldr r0, =ROMCON0<br /> stmia r0, {r1-r11}<br /> nop<br /> nop<br /> ldr r0, =IRQ_SVC_VECTOR<br /> ldr r1, =IRQ_SERVICE ;IRQ_SVC_VECTOR in ram, so set it after remap<br /> str r1, [r0]<br /> <br /> mov pc, r14 <br /><br />RemapMemPara<br /> DCD &12040060<br /> DCD &10842060<br /> DCD &10842060<br /> DCD &10842060<br /> DCD &10842060<br /> DCD &10842060<br /> DCD &10000398<br /> DCD &10040398<br /> DCD &10040398<br /> DCD &10040398<br /> DCD &ce2983fd <br /><br /> EXPORT ResetMemSet<br />ResetMemSet<br /> adr r0, ResetMemPara<br /> ldmia r0, {r1-r11}<br /> ldr r0, =ROMCON0<br /> stmia r0, {r1-r11}<br /> nop<br /> nop<br /> <br /> mov pc, r14 <br /> <br />ResetMemPara<br /> DCD &20000060<br /> DCD &00000060<br /> DCD &00000060<br /> DCD &00000060<br /> DCD &00000060<br /> DCD &00000060<br /> DCD &00000000<br /> DCD &00000000<br /> DCD &00000000<br /> DCD &00000000<br /> DCD &000083fd <br /><br />;*************************************************<br />InitInterrupt<br /> ldr r0, =INTMSK<br /> ldr r1, =0x3fffff<br /> str r1, [r0] ;disable all interrupt<br /> <br /> mov pc, r14 <br /><br />;*************************************************<br />InitPort<br /> ldr r0, =IOPMOD<br /> ldr r1, =1<br /> str r1, [r0] ;all input but p0 output<br /> <br /> ldr r0, =IOPCON<br /> ldr r1, =0<br /> str r1, [r0] ;disable XIRQ 0-3, dma req,ack, timer 0,1 output<br /> <br /> ldr r0, =IOPDATA<br /> ldr r1, [r0] ;read input data<br /> <br /> mov pc, r14 <br /><br />;*************************************************<br />InitTimer<br /> ldr r0, =TMOD<br /> ldr r1, =0<br /> str r1, [r0] ;disable timer 0,1<br /> <br /> mov pc, r14<br /><br />;*************************************************<br />UART_DIV_CNT0 EQU 26<br />UART_DIV_CNT1 EQU 0<br /><br />InitUart<br /> ldr r0, =ULCON0<br /> ldr r1, =DATA8b :OR: STOPb1 :OR PARITY_NO<br /> str r1, [r0]<br /> <br /> ldr r0, =UCON0<br /> ldr r1, =RX_STAT_INT|9<br /> str r1, [r0]<br /> <br /> ldr r0, =UBRDIV0<br /> ldr r1, =UART_DIV_CNT0<<4|UART_DIV_CNT1<br /> str r1, [r0] ;if UART_DIV_CNT1==xxx0 baud rate = MCLK/(UART_DIV_CNT0+1)/16<br /> ;if UART_DIV_CNT1==xxx1 baud rate = MCLK/(UART_DIV_CNT0+1)/16/16 <br /> ldr r0, =URXBUF0<br /> ldr r1, [r0] ;read rx data<br /> <br /> ldr r0, =ULCON1<br /> ldr r1, =DATA8b :OR: STOPb1 :OR PARITY_NO<br /> str r1, [r0]<br /> <br /> ldr r0, =UCON1<br /> ldr r1, =RX_STAT_INT|9<br /> str r1, [r0]<br /> <br /> ldr r0, =UBRDIV1<br /> ldr r1, =UART_DIV_CNT0<<4|UART_DIV_CNT1<br /> str r1, [r0] ;if UART_DIV_CNT1==xxx0 baud rate = MCLK/(UART_DIV_CNT0+1)/16<br /> ;if UART_DIV_CNT1==xxx1 baud rate = MCLK/(UART_DIV_CNT0+1)/16/16 <br /> ldr r0, =URXBUF1<br /> ldr r1, [r0] ;read rx data<br /> <br /> mov pc, r14<br /> <br />;************************************************* <br />InitStack<br /> mrs r0, cpsr<br /> bic r0, r0, #PSR_MODE_MASK<br /> <br /> orr r1, r0, #PSR_UNDEF_MODE|NO_INT<br /> msr cpsr_cxsf, r1 ;UndefMode<br /> ldr sp,=UndefStack<br /> <br /> orr r1, r0, #PSR_ABORT_MODE|NO_INT<br /> msr cpsr_cxsf, r1 ;AbortMode<br /> ldr sp, =AbortStack<br /> <br /> orr r1, r0, #PSR_IRQ_MODE|NO_INT<br /> msr cpsr_cxsf, r1 ;IRQMode<br /> ldr sp, =IRQStack<br /> <br /> orr r1, r0, #PSR_FIQ_MODE|NO_INT<br /> msr cpsr_cxsf, r1 ;FIQMode<br /> ldr sp, =FIQStack <br /> <br /> orr r1, r0, #PSR_SVC_MODE|NO_INT<br /> msr cpsr_cxsf, r1 ;SVCMode<br /> ldr sp, =SVCStack<br /> <br /> mov pc, r14<br /><br />;*************************************************<br /> EXPORT InitSystem <br />InitSystem<br /> mov r12, r14<br /> bl InitMemory<br /> bl InitStack<br /> bl InitPort<br /> bl InitUart<br /> bl InitTimer<br /> bl InitInterrupt<br />; ldr r0, =0x1000000 ;Cache Flush <br />; mov r1, #0<br />; mov r2, #256 <br />;1<br />; str r1, [r0], #4<br />; subs r2, r2, #1<br />; bne %B1 <br /> mov pc, r12 <br /> <br />;*************************************************<br />IRQ_SERVICE ;using I_ISPR register. <br /> IMPORT pIrqStart<br /> IMPORT pIrqFinish<br /> IMPORT pIrqHandler <br /> <br /> ;nop<br /> ;ldr r0, =TMOD<br /> ;ldr r1, [r0]<br /> ;and r1, r1, #&37<br /> ;str r1, [r0]<br /> <br /> ldr r4, =INTOFFSET<br /> ldr r4, [r4]<br /> mov r1, r4, lsr #2<br /> mov r0, #1<br /> mov r0, r0, lsl r1<br /> ldr r1, =INTPND<br /> str r0, [r1] ;clear interrupt pending bit<br /> ldr r1, =pIrqStart<br /> ldr r1, [r1]<br /> cmp r1, #0<br /> movne lr, pc ; .+8<br /> movne pc, r1 <br /> <br /> ldr r1, =pIrqHandler<br /> ldr r1, [r1]<br /> cmp r1, #0<br /> movne lr, pc<br /> movne pc, r1 <br /> <br /> ldr r1, =pIrqFinish<br /> ldr r1, [r1]<br /> cmp r1, #0<br /> movne lr, pc ; .+8<br /> movne pc, r1<br /> cmp r0, #0<br /> movne lr, pc<br /> movne pc, r0 <br /> <br /> ldmfd sp!, {r0} ;从IRQ返回<br /> msr spsr_cxsf, r0<br /> ldmfd sp!, {r0-r12, pc}^ <br />;*************************************************<br /> AREA HiVector, DATA, READWRITE<br /> <br />_RAM_END_ADDR EQU 0x01000000 <br /><br /> ^ (_RAM_END_ADDR-0x600) <br />UserStack # 256 ;xxxxxa00<br />SVCStack # 256 ;xxxxxb00<br />UndefStack # 256 ;xxxxxc00<br />AbortStack # 256 ;xxxxxd00<br />IRQStack # 256 ;xxxxxe00<br />FIQStack # 0 ;xxxxxf00<br /><br /><br /> MAP (_RAM_END_ADDR-0x100)<br />SYS_RST_VECTOR # 4 <br />UDF_INS_VECTOR # 4 <br />SWI_SVC_VECTOR # 4<br />INS_ABT_VECTOR # 4<br />DAT_ABT_VECTOR # 4<br />RESERVED_VECTOR # 4<br />IRQ_SVC_VECTOR # 4<br />FIQ_SVC_VECTOR # 4<br /><br /> EXPORT SYS_RST_VECTOR<br /> EXPORT UDF_INS_VECTOR<br /> EXPORT SWI_SVC_VECTOR<br /> EXPORT INS_ABT_VECTOR<br /> EXPORT DAT_ABT_VECTOR<br /> EXPORT RESERVED_VECTOR<br /> EXPORT IRQ_SVC_VECTOR<br /> EXPORT FIQ_SVC_VECTOR<br /> <br />;************************************************* <br /> END |
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