1.1 About the ARM architecture
The ARM architecture has been designed to allow very small, yet high-performence
implementations. The architectural simplicity of ARM processors leads to very small
implementations allow devices with very low power consumption.
The ARM is a Reduced Instruction Set Computer(RISC), as it incorporates these typical
RISC architecture features:
. a large uniform register file
. a load/store architecture, where data-processing operations only operate on register
contents, not directly on memory contents
. simple addressing modes, with all load/store address being determined from regsiter
contents and instruction fields only
. uniform and fixed-length instruction field, to simplify instruction decode.
In addition,the ARM architecture gives you:
. control over both the Arithmetic Logic Unit (ALU) and shifter in every
data-processing instruction to maximize the use of an ALU and a shifter
. auto-increment and auto-decrement addressing modes to optimize program loops
. Load and Store Multiple instructions to maximize data throughput.
. conditional execution of all instructions to maximize execution throughput.
These enhancements to a basic RISC architecture allow ARM processors to achieve a good
balance of high performance,low code size,low power consumption and low silicon area.
引自ARM官方的《ARM Architecture Reference Manual》
本人确实不太精通，但比较相信“老祖宗”的话。
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