|
`timescale 1ns / 1ps<br />////////////////////////////////////////////////////////////////////////////////<br />// Company: <br />// Engineer:<br />//<br />// Create Date: 10:46:31 03/20/07<br />// Design Name: <br />// Module Name: inout_module<br />// Project Name: <br />// Target Device: <br />// Tool versions: <br />// Description:<br />//<br />// Dependencies:<br />// <br />// Revision:<br />// Revision 0.01 - File Created<br />// Additional Comments:<br />// <br />////////////////////////////////////////////////////////////////////////////////<br />module inout_module(<br /> clk_125,<br /> rst_n,<br /> s,<br /> cl,<br /> d_out,<br /> d_in,<br /> mult_out0,<br /> mult_out1,<br /> mult_out2,<br /> mult_out3,<br /> mult_out4,<br /> mult_out5,<br /> mult_out6,<br /> mult_out7,<br /> mult_out8,<br /> mult_out9,<br /> mult_out10,<br /> mult_out11,<br /> mult_out12,<br /> mult_out13,<br /> mult_out14,<br /> mult_out15<br /> );<br /><br />input clk_125,rst_n,s,cl;<br />input [7:0] d_in;<br />input [7:0] mult_out0;<br />input [7:0] mult_out1;<br />input [7:0] mult_out2;<br />input [7:0] mult_out3;<br />input [7:0] mult_out4;<br />input [7:0] mult_out5;<br />input [7:0] mult_out6;<br />input [7:0] mult_out7;<br />input [7:0] mult_out8;<br />input [7:0] mult_out9;<br />input [7:0] mult_out10;<br />input [7:0] mult_out11;<br />input [7:0] mult_out12;<br />input [7:0] mult_out13;<br />input [7:0] mult_out14;<br />input [7:0] mult_out15;<br /><br />output [7:0] d_out;<br /><br />reg [7:0] d_out;<br />reg [4:0] cont;<br />reg [7:0] dout;<br /><br />always@(posedge clk_125 or negedge rst_n)begin<br /> if(!rst_n)<br /> begin<br /> cont <= 0;<br /> d_out <= 8'b0;<br /> dout <= 8'b0; <br /> end <br /> <br /> else<br /> begin<br /> if(~s)<br /> begin<br /> d_out <= d_in;<br /> end <br /> else if(s)<br /> begin<br /> cont <= cont + 1;<br /> d_out <= dout;<br /> end<br /> else if(cl)<br /> begin<br /> d_out <= 8'b0;<br /> dout <= 0;<br /> cont <= 0;<br /> end<br /> end<br /> end<br /><br />/*always@(posedge clk_125 or negedge rst_n)<br />begin<br /> if(!rst_n)<br /> cont <= 0;<br /><br /> else<br /> begin<br /> if(s)<br /> cont <= cont +1;<br /> else if(cl)<br /> cont <= 0;<br /> end<br />end */<br /><br />always@(cont or mult_out0 or mult_out1 or mult_out2 or mult_out3 or mult_out4 or mult_out5 or mult_out6 or mult_out7 or mult_out8 or mult_out9 or mult_out10 or mult_11 or mult_out12 or mult_out13 or mult_out14 or mult_15)<br /> case(cont)<br /> 5'b00001: dout = mult_out15;<br /> 5'b00010: dout = mult_out14;<br /> 5'b00011: dout = mult_out13;<br /> 5'b00100: dout = mult_out12;<br />line119 5'b00101: dout = mult_out11;<br /> 5'b00110: dout = mult_out10;<br /> 5'b00111: dout = mult_out9;<br /> 5'b01000: dout = mult_out8;<br /> 5'b01001: dout = mult_out7;<br /> 5'b01010: dout = mult_out6;<br /> 5'b01011: dout = mult_out5;<br /> 5'b01100: dout = mult_out4;<br /> 5'b01101: dout = mult_out3;<br /> 5'b01110: dout = mult_out2;<br /> 5'b01111: dout = mult_out1;<br /> default : dout = mult_out0;<br /> endcase <br />endmodule<br />综合时报错如下：<br />ERROR:HDLCompilers:26 - "inout_module.v" line 119 expecting 'endcase', found '\241'<br />ERROR:HDLCompilers:26 - "inout_module.v" line 119 expecting 'endmodule', found '5'<br />ERROR: XST failed<br /> |
|
楼主
