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VHDL程序求救<br />library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br />--use ieee.std_logic_arith.all;<br />entity frqctl is<br />port(frq_chg:in std_logic_vector(3 downto 0);<br /> q_out:out integer range 0 to 100000);--std_logic_vector(15 downto 0));<br />end frqctl;<br />architecture a of frqctl is<br />begin<br />--temp<=10000;--"0010011100010000";<br />process (frq_chg)<br />variable temp:integer range 1000 to 20000;--std_logic_vector(15 downto 0);<br />--variable b:integer ;<br />begin<br />temp:=10000;<br />if frq_chg(0)='0' then<br />temp:=temp+1;<br />elsif frq_chg(1)='0' then<br />temp:=temp-1;<br />elsif frq_chg(2)='0' then <br />temp:=temp+100;<br />elsif frq_chg(3)='0' then<br />temp:=temp-100;<br />end if;<br />--b:=1/temp;<br />q_out<=100000000/temp;<br />end process;<br />end a;<br />编译时总是出现right operand of "divide"operator must be a power of 2<br />哪位高人帮忙指点呀~~ |
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