自学FPGA没多久，对<=,=>,<=这几个符号老是搞混，比如下面这段程序中的语句
entity key_led is
port (
key_in : in std_logic_vector (3 downto 0); --KEY INPUT
led_out : out std_logic_vector (5 downto 0) --LED OUTPUT
);
end entity;
architecture key_led_arch of key_led is
begin
process(key_in)
begin
led_out <= (others => '1'); 就是这段语句，到底是实现什么功能
case key_in is
when "1110" => led_out <= "111110";
when "1101" => led_out <= "111100";
when "1011" => led_out <= "111000";
when "0111" => led_out <= "110000";
when others => NULL;
end case;
end process;
end architecture; |
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楼主
