void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins
P11SEL |= 0x07; // P11.0,1,2 for debugging purposes.
P2SEL |= 0x0E; // P2.1 - P2.3 option select 0000 1110
P2DIR |= 0x0E; // P2.1 - P2.3 outputs
P4DIR |= 0x10; // P1.0 - Outputs
TA1CCTL0 = OUTMOD_4 + CCIE; // CCR0 toggle, interrupt enabled
TA1CCTL1 = OUTMOD_4 + CCIE; // CCR1 toggle, interrupt enabled
TA1CCTL2 = OUTMOD_4 + CCIE; // CCR2 toggle, interrupt enabled
TA1CTL = TASSEL__ACLK + MC__CONTINOUS + TACLR + TAIE; // ACLK, contmode, clear TAR,
// interrupt enabled
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, interrupts enabled
__no_operation(); // For debugger
}
// Timer1 A0 interrupt service routine
#pragma vector=TIMER1_A0_VECTOR
__interrupt void Timer_A0 (void)
{
TA1CCR0 += 4; // Add Offset to CCR0
}
// Timer_A3 Interrupt Vector (TAIV) handler
#pragma vector=TIMER1_A1_VECTOR
__interrupt void TIMER1_A1_ISR(void)
{
switch(__even_in_range(TA1IV,14))
{
case 0: break;
case 2: TA1CCR1 += 16; // Add Offset to CCR1
break;
case 4: TA1CCR2 += 100; // Add Offset to CCR2
break;
case 6: break; // CCR3 not used
case 8: break; // CCR4 not used
case 10: break; // CCR5 not used
case 12: break; // Reserved not used
case 14: P4OUT ^= 0x10; // overflow
break;
default: break;
}
} |
|
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