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从论坛上得到过不少有价值的资料，今天将自己在学习ＤＳＰ的过程中的一点小收获给大家分享一下。<br />1、在进行vc5502倍频操作时，遇到的第一个问题是，不知道如何访问PLL的控制寄存器。首先PLL的控制寄存器是被分配在I/O space，对I/O space的寄存器访问不像对cpu寄存器，可以直接进行声明和访问，对I/O space的寄存器需要用到关键词ioport来声明。格式举例如下：<br />#define PLLCSR ((volatile ioport int *)0X1C80)<br />该语句是把0x1c80定义为一个I/O空间的指针量并用PLLCSR来替换。在对I/O空间的寄存器0x1c80进行访问时与对一个指针变量的操作相同。格式如下<br /> * PLLCSR=....或….= *PLLCSR<br />2、在正确的访问寄存器的基础上，设置dsp的PLL要满足一定的规则(该部分内容可以参见vc5502的datasheet) ：<br />The following procedure must be followed to change or to set the PLL to a specific value:<br />1. Switch to bypass mode by setting the PLLEN bit to 0.<br />2. Set the PLL to its reset state by setting the PLLRST bit to 1.<br />3. Change the PLL setting through the PLLM and PLLDIV0 bits.<br />4. Wait for 1 μs.<br />5. Release the PLL from its reset state by setting PLLRST to 0.<br />6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.<br />7. Switch back to PLL mode by setting the PLLEN bit to 1.<br />Note：The frequency of the C55x Subsystem Clock Group can be up to 300 MHz for the TMS320VC5502-300 and up to 200 MHz for the TMS320VC5502-200.<br /><br />Program example<br /><br />void init_fuc() <br />{ u16 i;<br /> *PLLCSR=0X0048; //PLLEN=0,PLLRST=1(PLL asserted)<br /> *PLLM=0x0003; //phrequency 2 TIMES<br /> *PLLDIV0=0x8000; //enable PLLDIV0 and divided by 1<br /> for(i=0;i<500;i++); //waiting> 1us<br /> *PLLCSR=0X0040; //PLLRST=0(PLL released) <br /> while((*PLLCSR & 0x0020)==0);//polling the lock bit until it is changed to 1<br /> *PLLCSR=0X0041; //PLLare not bypassed <br />} <br /> |
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