时钟时序分析?
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FPGA论坛 | izefei 2011-5-26 | 16 2233 | hjjnet 2011-5-28 19:11 |
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Xilinx FPGA设计约束的分类 | FPGA论坛 | ChaiTF 2012-12-24 | 10 1546 | gaochy1126 2012-12-25 23:06 |
Allegro 求助 | EDA 技术 | LH158 2010-6-28 | 1 1709 | lu150 2010-7-5 18:19 |
玩转Vivado之Timing Constraints
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FPGA论坛 | rousong1989 2016-1-11 | 0 669 | rousong1989 2016-1-11 16:24 |
UCF to XDC (Timing Constraints in Vivado) | EDA 技术 | 51xlf 2016-1-27 | 1 1794 | gaochy1126 2016-1-31 21:25 |