本帖最后由 y18370990546 于 2020-3-2 20:09 编辑
C64xx系列，DSP采用MCBSP和EDMA模式进行64通道数据收发测试，
采用CLKX、CLKR为外部输入4M, FRS、FRX为外部输入8K频率，
手动将DR和DX引脚短接构成回环。
Mcbsp每帧发送8位的64个数据，数据为（0、1、2........、63）
测试过程中，EDMA数据接能接收到（0-63），但多了很多0xff的数据，不知道为何？EDMA接收中断进入也较异常（手动点击串口的寄存器才能进）
此芯片最多有128个通道，难道是其余64个通道来的数据吗?
当由DSP这边内部提供时钟时，发现时钟脉冲是一段一段的（一段正常，一段电平为高），大概是下面这样。
求教各位
MCBSP_SPCR_RMK //Serial Port Control Register (SPCR)
(
MCBSP_SPCR_FREE_NO, // Serial clock free running mode(FREE)
MCBSP_SPCR_SOFT_NO, // Serial clock emulation mode(SOFT)
MCBSP_SPCR_FRST_YES, // Frame sync generator reset(FRST)
MCBSP_SPCR_GRST_YES, // Sample rate generator reset(GRST)
MCBSP_SPCR_XINTM_XRDY, // Transmit interrupt mode(XINTM)
MCBSP_SPCR_XSYNCERR_NO, // Transmit synchronization error
MCBSP_SPCR_XRST_YES, // Transmitter reset(XRST)
MCBSP_SPCR_DLB_OFF, // Digital loopback(DLB) mode
MCBSP_SPCR_RJUST_DEFAULT, // 右边有效数字位，高位填0
MCBSP_SPCR_CLKSTP_DISABLE, // Clock stop(CLKSTP) mode
MCBSP_SPCR_DXENA_OFF, // DX Enabler(DXENA) -Extra delay for DX turn-on time.
MCBSP_SPCR_RINTM_RRDY, // Receive interrupt(RINT) mode
MCBSP_SPCR_RSYNCERR_NO, // Receive synchronization error(RSYNCERR)
MCBSP_SPCR_RRST_YES // Receiver reset(RRST)
),
MCBSP_RCR_RMK // Receive Control Register (RCR)
(
MCBSP_RCR_RPHASE_SINGLE, // Receive phases
MCBSP_RCR_RFRLEN2_OF(0), // Receive frame length in phase 2(RFRLEN2)
MCBSP_RCR_RWDLEN2_8BIT, // Receive element length in phase 2(RWDLEN2)
MCBSP_RCR_RCOMPAND_MSB, // Receive companding mode (RCOMPAND)
MCBSP_RCR_RFIG_NO, // Receive frame ignore(RFIG)
MCBSP_RCR_RDATDLY_0BIT, // Receive data delay(RDATDLY)
MCBSP_RCR_RFRLEN1_OF(63), // Receive frame length in phase 1(RFRLEN1)
MCBSP_RCR_RWDLEN1_8BIT, // Receive element length in phase 1(RWDLEN1)
MCBSP_RCR_RWDREVRS_DISABLE // Receive 32-bit bit reversal feature.(RWDREVRS)
),
MCBSP_XCR_RMK //Transmit Control Register (XCR)
(
MCBSP_XCR_XPHASE_SINGLE, // Transmit phases
MCBSP_XCR_XFRLEN2_OF(0), // Transmit frame length in phase 2(XFRLEN2)
MCBSP_XCR_XWDLEN2_8BIT, // Transmit element length in phase 2
MCBSP_XCR_XCOMPAND_MSB, // Transmit companding mode(XCOMPAND)
MCBSP_XCR_XFIG_NO, // Transmit frame ignore(XFIG)
MCBSP_XCR_XDATDLY_0BIT, // Transmit data delay(XDATDLY)
MCBSP_XCR_XFRLEN1_OF(63), // Transmit frame length in phase 1(XFRLEN1)
MCBSP_XCR_XWDLEN1_8BIT, // Transmit element length in phase 1(XWDLEN1)
MCBSP_XCR_XWDREVRS_DISABLE // Transmit 32-bit bit reversal feature
),
/*
MCBSP_SRGR_RMK //MCBSP_SRGR_DEFAULT,
(
MCBSP_SRGR_GSYNC_FREE,
MCBSP_SRGR_CLKSP_RISING,
MCBSP_SRGR_CLKSM_INTERNAL,
MCBSP_SRGR_FSGM_DXR2XSR,
MCBSP_SRGR_FPER_DEFAULT,
MCBSP_SRGR_FWID_DEFAULT,
MCBSP_SRGR_CLKGDV_OF(64)
),
*/
MCBSP_SRGR_DEFAULT,
MCBSP_MCR_RMK //选择多通道模式
(
MCBSP_MCR_XMCME_ENHANCED, //1
MCBSP_MCR_XPBBLK_DEFAULT,
MCBSP_MCR_XPABLK_DEFAULT,
MCBSP_MCR_XMCM_ENMASK,
MCBSP_MCR_RMCME_ENHANCED, //1
MCBSP_MCR_RPBBLK_DEFAULT,
MCBSP_MCR_RPABLK_DEFAULT,
MCBSP_MCR_RMCM_ELDISABLE
),
MCBSP_RCERE0_OF(0xffffffff), //使能前面64个通道的收发
MCBSP_RCERE1_OF(0xffffffff),
MCBSP_RCERE2_OF(0x00000000),
MCBSP_RCERE3_OF(0x00000000),
MCBSP_XCERE0_OF(0xffffffff),
MCBSP_XCERE1_OF(0xffffffff),
MCBSP_XCERE2_OF(0x00000000),
MCBSP_XCERE2_OF(0x00000000),
MCBSP_PCR_RMK //serial port pin control register(PCR)
(
MCBSP_PCR_XIOEN_SP, // Transmitter in general-purpose I/O mode
MCBSP_PCR_RIOEN_SP, // Receiver in general-purpose I/O mode
MCBSP_PCR_FSXM_EXTERNAL, // Transmit frame synchronization mode
MCBSP_PCR_FSRM_EXTERNAL, // Receive frame synchronization mode
MCBSP_PCR_CLKXM_INPUT, // Transmitter clock mode (CLKXM)
MCBSP_PCR_CLKRM_INPUT, // Receiver clock mode (CLKRM)
MCBSP_PCR_CLKSSTAT_0, // CLKS pin status(CLKSSTAT)
MCBSP_PCR_DXSTAT_0, // DX pin status(DXSTAT)
MCBSP_PCR_FSXP_ACTIVELOW, // Transmit frame synchronization polarity(FSXP)
MCBSP_PCR_FSXP_ACTIVELOW, // Receive frame synchronization polarity(FSRP)
MCBSP_PCR_CLKXP_FALLING, // Transmit clock polarity(CLKXP)
MCBSP_PCR_CLKRP_RISING // Receive clock polarity(CLKRP)
)
};
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