问答

[url=/data/attachment/album/202408/12/142733v7ang1vo1vb1aooo.png][img]/data/attachment/album/202408/12/142733v7ang1vo1vb1aooo.png[/img][/url] 是否可以增加 HSE PLL相关设定 RCC例程

#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) /* select HXTAL/2 as clock source */ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */ RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); //RCU_CFG0 |= RCU_PLL_MUL27; //这里CK_HXTAL为16MHz,所以计算倍频得13.5，那么应该选RCU_PLL_MUL13还是RCU_PLL_MUL14呢？ RCU_CFG0 |= RCU_PLL_MUL13;//？？RCU_PLL_MUL14？？

AT32F403AVCT7 外部晶振8MHZ PLL倍频到200MHZ 在串口3设9600波特率 理论一个字节的时间时1.04MS 实测一个字节1.14MS 这个请问大佬们有没有遇到同样问题 ，MOC端口主频输出也示波器测过在200MHZ有那么点波动

设置主频为60M怎么设置，用内部8M倍频，但PLL中没有15倍频，选择PLL1或PLL2，然后配置好像有问题，仿真卡在了时钟初始化，求该如何配置？

8M外部晶振 PLL 168MUSART0实际波特率只有设置波特率的三分之一而且最后一个字节不对（全1）或丢失 请问有人有过类似问题吗

我在配置HC32F460的时钟，遇到了一个比较鬼畜的问题。我按照如下代码设置了时钟，但奇怪的是，我在硬件上端接晶振引脚，按说芯片会宕机才对，但芯片居然毫无影响，继续运行。想麻烦大家帮我看看，是我哪里设置的不对 [color=#d4d4d4][backcolor=rgb(30, 30, 30)][font=Menlo, Monaco, "][size=12px] [color=#569cd6]void[/color] [color=#dcdcaa]SystemClk_Init[/color]([color=#569cd6]void[/color]) { [color=#4ec9b0]stc_clk_sysclk_cfg_t[/color] [color=#9cdcfe]stcSysClkCfg[/color]; [color=#4ec9b0]stc_clk_xtal_cfg_t[/color] [color=#9cdcfe]stcXtalCfg[/color]; [color=#4ec9b0]stc_clk_mpll_cfg_t[/color] [color=#9cdcfe]stcMpllCfg[/color]; [color=#569cd6]MEM_ZERO_STRUCT[/color]([color=#9cdcfe]stcSysClkCfg[/color]); [color=#569cd6]MEM_ZERO_STRUCT[/color]([color=#9cdcfe]stcXtalCfg[/color]); [color=#569cd6]MEM_ZERO_STRUCT[/color]([color=#9cdcfe]stcMpllCfg[/color]); [color=#6a9955]/* Set bus clk div. */[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enHclkDiv[/color] = [color=#4fc1ff]ClkSysclkDiv1[/color]; [color=#6a9955]// 168MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enExclkDiv[/color] = [color=#4fc1ff]ClkSysclkDiv2[/color]; [color=#6a9955]// 84MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk0Div[/color] = [color=#4fc1ff]ClkSysclkDiv1[/color]; [color=#6a9955]// 168MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk1Div[/color] = [color=#4fc1ff]ClkSysclkDiv2[/color]; [color=#6a9955]// 84MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk2Div[/color] = [color=#4fc1ff]ClkSysclkDiv4[/color]; [color=#6a9955]// 42MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk3Div[/color] = [color=#4fc1ff]ClkSysclkDiv4[/color]; [color=#6a9955]// 42MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk4Div[/color] = [color=#4fc1ff]ClkSysclkDiv2[/color]; [color=#6a9955]// 84MHz[/color] [color=#dcdcaa]CLK_SysClkConfig[/color](&[color=#9cdcfe]stcSysClkCfg[/color]); [color=#6a9955]/* Switch system clock source to MPLL. */[/color] [color=#6a9955]/* Use Xtal as MPLL source. */[/color] [color=#9cdcfe]stcXtalCfg[/color].[color=#9cdcfe]enMode[/color] = [color=#4fc1ff]ClkXtalModeOsc[/color]; [color=#9cdcfe]stcXtalCfg[/color].[color=#9cdcfe]enDrv[/color] = [color=#4fc1ff]ClkXtalLowDrv[/color]; [color=#9cdcfe]stcXtalCfg[/color].[color=#9cdcfe]enFastStartup[/color] = [color=#4fc1ff]Disable[/color]; [color=#dcdcaa]CLK_XtalConfig[/color](&[color=#9cdcfe]stcXtalCfg[/color]); [color=#dcdcaa]CLK_XtalCmd[/color]([color=#4fc1ff]Enable[/color]); [color=#6a9955]/* MPLL config. */[/color] [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]pllmDiv[/color] = [color=#b5cea8]1u[/color]; [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]plln[/color] = [color=#b5cea8]42u[/color]; [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]PllpDiv[/color] = [color=#b5cea8]2u[/color]; [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]PllqDiv[/color] = [color=#b5cea8]2u[/color]; [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]PllrDiv[/color] = [color=#b5cea8]2u[/color]; [color=#dcdcaa]CLK_SetPllSource[/color]([color=#4fc1ff]ClkPllSrcXTAL[/color]); [color=#dcdcaa]CLK_MpllConfig[/color](&[color=#9cdcfe]stcMpllCfg[/color]); [color=#6a9955]/* flash read wait cycle setting */[/color] [color=#dcdcaa]EFM_Unlock[/color](); [color=#dcdcaa]EFM_SetLatency[/color]([color=#569cd6]EFM_LATENCY_4[/color]); [color=#dcdcaa]EFM_Lock[/color](); [color=#6a9955]/* Enable MPLL. */[/color] [color=#dcdcaa]CLK_MpllCmd[/color]([color=#4fc1ff]Enable[/color]); [color=#6a9955]/* Wait MPLL ready. */[/color] [color=#c586c0]while[/color] ([color=#4fc1ff]Set[/color] != [color=#dcdcaa]CLK_GetFlagStatus[/color]([color=#4fc1ff]ClkFlagMPLLRdy[/color])) { } [color=#6a9955]/* Switch system clock source to MPLL. */[/color] [color=#dcdcaa]CLK_SetSysClkSource[/color]([color=#4fc1ff]ClkSysSrcXTAL[/color]); } [/size][/font][/backcolor][/color]

我直接在固件库里做了修改，不知道为何不行 static void SetSysClockTo48M(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; // 把RCC外设初始化成复位状态，这句是必须的 RCC_Reset(); //使能HSI RCC_HSICmd(ENABLE); // 只有 HSI就绪之后则继续往下执行 if (RCC_GetFlagStatus(RCC_FLAG_HSISTBL )) { //----------------------------------------------------------------------// FLASH->ACR = FLASH_ACR_DEFAULT(FLASH_ACR_LATENCY_1); //----------------------------------------------------------------------// // AHB预分频因子设置为1分频，HCLK = SYSCLK RCC_AHBCLKConfig(RCC_SYSCLK_Div1); // APB2预分频因子设置为1分频，PCLK2 = HCLK RCC_APB2CLKConfig(RCC_AHBCLK_Div1); // APB1预分频因子设置为1分频，PCLK1 = HCLK RCC_APB1CLKConfig(RCC_AHBCLK_Div1); // 设置PLL时钟来源为HSE，设置PLL倍频因子 // PLLCLK = 4MHz * pllmul RCC_PLLConfig(RCC_PLLRefClk_HSI_Div2, 12,RCC_Range_LessEqual_72Mhz); //------------------------------------------------------------------// // 开启PLL RCC_PLLCmd(ENABLE); // 等待 PLL稳定 while (RCC_GetFlagStatus(RCC_FLAG_PLLSTBL) == RESET) { } // 当PLL稳定之后，把PLL时钟切换为系统时钟SYSCLK RCC_SYSCLKConfig(RCC_SYSCLKSelction_HSI); // 读取时钟切换状态位，确保PLLCLK被选为系统时钟 while (RCC_GetSYSCLKSelction() != 0x08) { } } else { while (1) { } }

原先使用的STM32030C8，代码也是用STM的时标准库写的，直接换航顺的HK32F030C8上去，程序运行到时钟配置时不行了。时钟配置代码： static void RCC_Configuration(void) { u16 i; RCC_DeInit(); /*使能HSI */ RCC_HSICmd(ENABLE); /*设置PLL时钟源及倍频系数*/ RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_12); //16MHz（RCC_PLLMul_4），36MHz（RCC_PLLMul_9），48MHz（RCC_PLLMul_12）。 /*使能PLL */ RCC_PLLCmd(ENABLE); i = 1000; while((RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) && (--i > 0)); /*设置系统时钟（SYSCLK） */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); SystemCoreClockUpdate(); } 将RCC_PLLMul_12改为RCC_PLLMul_9或以下时，程序运行正常。RCC_PLLMul_10及以上时程序就不行了。