1)顶层模块
[url=][/url]
module AsyncFIFO #(parameter ASIZE = 4, //地址位宽 parameter DSIZE = 8) //数据位宽 ( input [DSIZE-1:0] wdata, input winc, wclk, wrst_n, //写请求信号,写时钟,写复位 input rinc, rclk, rrst_n, //读请求信号,读时钟,读复位 output [DSIZE-1:0] rdata, output wfull, output rempty );wire [ASIZE-1:0] waddr, raddr;wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr; /************************************************************* In order to perform FIFO full and FIFO empty tests using * this FIFO style, the read and write pointers must be* passed to the opposite clock domain for pointer comparison*************************************************************//*在检测“满”或“空”状态之前,需要将指针同步到其它时钟域时,使用格雷码,可以降低同步过程中亚稳态出现的概率*/sync_r2w I1_sync_r2w( .wq2_rptr(wq2_rptr), .rptr(rptr), .wclk(wclk), .wrst_n(wrst_n));sync_w2r I2_sync_w2r ( .rq2_wptr(rq2_wptr), .wptr(wptr), .rclk(rclk), .rrst_n(rrst_n));/** DualRAM */DualRAM #(DSIZE, ASIZE) I3_DualRAM( .rdata(rdata), .wdata(wdata), .waddr(waddr), .raddr(raddr), .wclken(winc), .wclk(wclk)); /** 空、满比较逻辑*/rptr_empty #(ASIZE) I4_rptr_empty( .rempty(rempty), .raddr(raddr), .rptr(rptr), .rq2_wptr(rq2_wptr), .rinc(rinc), .rclk(rclk), .rrst_n(rrst_n));wptr_full #(ASIZE) I5_wptr_full( .wfull(wfull), .waddr(waddr), .wptr(wptr), .wq2_rptr(wq2_rptr), .winc(winc), .wclk(wclk), .wrst_n(wrst_n));endmodule[url=][/url]
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