谢谢 FSL_TICS_ZJJ的回答，但是你回复里描述的应该是 CAN 的 bit timing。
KEA128RM文档中关于CAN的 time stamp 或者说是时间戳的描述不多，说是使用一个internal timer来count，在 tx message与rx message的 EOF时间段内把 timer的值给到寄存器中，如下有关timer enable的描述
This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the
timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the
active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to
the highest bytes (0x000E, 0x000F) in the appropriate buffer. In loopback mode no receive timestamp is
generated. The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization
mode.
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