library ieee
USE IEEE_STD_LOGIC_1164.ALL;
USE IEEE_STD_LOGIC_ARITH.ALL;
USE IEEE_STD_LOGIC_UNSIGNED.ALL;entity myjkff is
port(j,k,clr:in std_logic;
clk:in std_logic;
q,qn:buffer std_logic);
end myjkff;
architecture one of myjkff is
begin
process(j,k,clr,clk)
variable jk:std_logic_vector(1 downto 0);
begin
jk:=(j & k);
if clr='0'then
q<='0';
qn<='1';
elsif clk'event and clk='0' then
case jk is
when "00"=> q<=q; qn <=qn;
when "01"=> q<='0'; qn <='1';
when "10"=> q<='1'; qn <='0';
when "11"=> q<='1'; qn <='1';
when others=> null;
end case;
end if;
end process;
end one;
我是新手，上面是我编写的JK触发器的VHDL语言设计,但是编译是出现了16个错误,我怎么也不知道如何改正，请各位老师帮我分析改正，谢谢
1、Error (10170): Verilog HDL syntax error at jk.v(2) near text "IEEE_STD_LOGIC_1164"; expecting ";", or ",", or "-"
2、Error (10170): Verilog HDL syntax error at jk.v(3) near text "."; expecting ";", or ","
3、Error (10839): Verilog HDL error at jk.v(3): declaring global objects is a SystemVerilog feature
4、Error (10170): Verilog HDL syntax error at jk.v(4) near text "."; expecting ";", or ","
5、Error (10839): Verilog HDL error at jk.v(4): declaring global objects is a SystemVerilog feature
6、Error (10170): Verilog HDL syntax error at jk.v(4) near text "is"; expecting ";", or ","
7、Error (10170): Verilog HDL syntax error at jk.v(5) near text ":"; expecting ";", or ","
8、Error (10839): Verilog HDL error at jk.v(6): declaring global objects is a SystemVerilog feature
9、Error (10839): Verilog HDL error at jk.v(7): declaring global objects is a SystemVerilog feature
10、Error (10170): Verilog HDL syntax error at jk.v(8) near text "end"; "end" without "begin"
11、Error (10839): Verilog HDL error at jk.v(8): declaring global objects is a SystemVerilog feature
12、Error (10170): Verilog HDL syntax error at jk.v(9) near text "of"; expecting ";", or ","
13、Error (10149): Verilog HDL Declaration error at jk.v(11): identifier "k" is already declared in the present scope
14、Error (10149): Verilog HDL Declaration error at jk.v(11): identifier "clr" is already declared in the present scope
15、Error (10170): Verilog HDL syntax error at jk.v(11) near text ")"; expecting ";", or ","
16、Error: Quartus II Analysis & Synthesis was unsuccessful. 16 errors, 0 warnings
请各位老师帮我分析改正 |
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