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求教，本人新学CPLD不久，用Verilog编写了一段Quartus II程序，通过单片机和CPLD对继电器开关进行开合控制，CPLD选用的是EPM7512AETC144-10。在仿真的时候，功能仿真出现错误，时序仿真确是正确的，让我比较困惑。求教各位前辈高手指点指点。 <br />程序如下： <br />module zc(in,data,out,rst); <br />input data,rst; <br />input [1:0]in; <br />output [3:0]out; <br />reg [3:0]out,add,add1,latch; <br /><br /><br />always@(in or data or rst or latch ) <br /> begin <br /> if(rst) <br /> begin <br /> add = 4'b1111; <br /> add1 = 4'b1111; <br /> latch= 4'b1111; <br /> out = 4'b1111; <br /> end <br /> else <br /> begin <br /> if(!data) <br /> begin <br /> case(in) <br /> 2'b00:add=4'b1110; <br /> 2'b01:add=4'b1101; <br /> 2'b10:add=4'b1011; <br /> 2'b11:add=4'b0111; <br /> endcase <br /> add1=add&latch; <br /> //latch=add1; <br /> out[0]=add1[0]?1'b1:1'b0; <br /> out[1]=add1[1]?1'b1:1'b0; <br /> out[2]=add1[2]?1'b1:1'b0; <br /> out[3]=add1[3]?1'b1:1'b0; <br /> latch=out; <br /> end <br /> else <br /> begin <br /> case(in) <br /> 2'b00:begin add=4'b1110;end <br /> 2'b01:begin add=4'b1101;end <br /> 2'b10:begin add=4'b1011;end <br /> 2'b11:begin add=4'b0110;end <br /> endcase <br /> out[0]=add[0]?latch[0]:1'b1; <br /> out[1]=add[1]?latch[1]:1'b1; <br /> out[2]=add[2]?latch[2]:1'b1; <br /> out[3]=add[3]?latch[3]:1'b1; <br /> latch=out; <br /> end <br /> <br /> end <br /> end <br />endmodule <br />我在综合编译的时候，出现2个警告：<br />Warning: Verilog HDL Always Construct warning at zc.v(8): variable add1 may not be assigned a new value in every possible path through the Always Construct. Variable add1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design. <br />Warning: Verilog HDL Always Construct warning at zc.v(8): variable latch may not be assigned a new value in every possible path through the Always Construct. Variable latch holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design. <br />敬请指教。 |
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