Finite state machine's VHDL optimization design
Compares with other hardware description language, VHDL has the following characteristic:
The function is strong and the design be vivid.The VHDL has the function strong language structure, can describe a complicated logic control with the simple and direct and explicit source code.It has a multi-layer design description function, in multiple layers thin turn, finally directly born electric circuit class description.The VHDL supports synchronous electric circuit, difference's tread electric circuit with random the design of electric circuit, this be the other hardware description although the language can't compare to.The VHDL still supports various design method, since support from the bottom upward design, support again from the design of crest declivity;Since the support mold piece turns a design, support layer's turn a design again. Support extensively and be easy to a modification.Because the VHDL has already become IEEE standard the norm of hardware description language, most EDA tools almost support VHDL currently, this is VHDL of further expansion with extensively applied lay foundation.In the design process of the hardware electric circuit, the main design document is the source code which writes with the VHDL, the VHDL easily reads with the structure turn, so be easy to a modification design.
The strong system hardware describes ability.The VHDL has a multi-layer design description function, since can describe system class electric circuit, can describe door class electric circuit again.And description since can adopt a behavior description, deposit a machine to deliver description or structure description, can also adopt the hybrid description of threes mixture.Moreover, VHDL support is inertial to delay and deliver to delay, can also accurately build up hardware electric circuit model.VHDL support prepare definite of with from definition of data type, bring hardware description a bigger freedom degree, make design the personnel can expediently establish the system model of high time. The independence is at the design of spare part, have nothing to do with the craft.Don't need to consider a choice completion the spare part of design first while designing a personnel to carry on a design with the VHDL, can concentrate energy to carry on design of excellent turn.When the design description complete after, can carry out its function with various different spare part structure. Very strong transplantation ability.The VHDL is a kind of hardware description for standardize language, the same of design description can be support by the different tool and make to design to describe of the transplantation make possible.
Be easy to a share and reply to use.The VHDL adoption can build up various mold piece that can again make use of according to the design method of database(Library).These canned in advance design or use to design a medium backup mold a piece before and depositted these to the database in, can be in laterly of the design carry on replying to use, can make the design result be design the personnel's to carry on exchanges and share, decrease hardware electric circuit design.
1.introduction
Current take the hardware description language as the tool, the logical component is getting more and more widespread for the carrier system design. In the design, the state machine is most typical, applies the most widespread electric circuit module, it in the running rate highly effective, execution time's determinism and the redundant reliable aspect appears the formidable superiority. The state machine and the design technique level has decided the system design fit and unfit quality. How to design the question which an optimized the state machine is we must face. This article will discuss state machine compilation each step to optimize the role which the state machine plays.
2.state machine's classification
The state machine by the condition register and the combinatory logic electric circuit constitution, can according to the condition which establishes in advance carry on the condition shift according to the control signal, is the coordinated coherent signal movement, completes the specific operation the control center. The state machine may divide into Moore and the Mealy two fundamental types. When design which method selects the condition confidential to decide according to the design special details that the output only decides the rule by the current condition value to select Moore, the input signal and the condition value decided together loses the origin to select the Mealy state machine. When design usually follows the following several points in the structure: Various modules only describe a state machine; Will have nothing to do with logic to reduce to few; Separates the condition register from other logic.
3.condition value encoding method
Usually when designs the state machine, the condition encoding method's choice is very important, elects not well, possibly will cause the speed to be too slow or to take the too many logical resources. In the actual design, must consider that various factor chooses the most appropriate encoding method.
3.1enumeration type definition state value
In the design state machine's condition value defines as the enumeration type, when the synthesis generally transforms as the binary sequence, therefore and the binary system encoding method is essentially same. The actual need trigger's number is the actual condition take 2 as the bottom logarithm. This encoding method is simplest, the comprehensive backing resister amount used are few, the surplus condition are least, its synthesis efficiency and the electric circuit speed will have the enhancement in the certain extent. But in the phase transition process, the condition register's top digit turn over and the low position switching time is inconsistent, will like this have the state of transition, if state machine's condition night-watch will be many, will have the state of transition probability to be bigger. Therefore suits the order of complexity low design.
3.2 gray code expression condition value
The gray code code, namely the neighboring two condition's code only then a difference, this causes to use the gray code expression condition value the state machine, may in the great degree eliminate the state of transition which causes by the transmission time delay. This way causes skips when the adjacent state, only then a change, reduces has had the state of transition probability, But when the phase transition has many kinds of ways, is unable guarantees when condition skipping to have a change. Therefore to a certain extent, the gray code code is the binary one kind of distortion, the overall thought is consistent.
3.3“ONE-HOT” the condition value codes
The One-hot encoding method is uses N trigger to realize N condition state machine, each condition indicated by a trigger, in random time, only then 1 effectiveness, this is also called “hot”, the trigger is `1 ', other triggers set at `0 '. This kind of structure's state machine its stability surpasses the general structure the state machine, but it takes the resources are more. Its simple encoding method simplified the condition decoding logic, raised the phase transition speed, suits in applies in FPGA.
3.4 surplus conditions and fault-tolerant technology
In the state machine design, will have the massive surplus conditions inevitably. If does not carry on reasonable processing to the surplus condition, the state machine possibly enters the uncertain condition, the consequence is appears to the outside short out of control or is unable to get rid of the surplus condition throughout to lose the normal function. Therefore, to surplus condition's processing, namely the fault-tolerant technology's application is the question which must give careful consideration. But, surplus condition's processing or the same degree consumes the logical resource, therefore the designer is selecting the state machine structure, the condition encoding method, fault-tolerant technical and system's working speed and the availability of resources aspect needs to make the balance to compare, adapts own design requirements. The surplus condition's shift whereabouts have the following several kinds approximately:①Changes over to the idling condition, the waiting next work mission arrival;②Changes over to condition which assigns, carries out the specific task;③Changes over to the pre-definition the special processing wrong condition, like early warning condition.
Regarding the first two encoding method may the unnecessary condition formulation, perform in the later sentence to process. The processing method has 2 kinds:①Makes the explicit phase transition instruction in the sentence to each illegal state;②To the condition which had not mentioned makes unification processing using the others sentence. Will increase regarding the One-hot encoding method its surplus condition number along with the effective condition number assumes the index type sharp increase, cannot use the above processing method. In view of the fact that the One-hot encoding method's characteristic, any is more than 1 trigger is “1” the condition is the illegal state. Therefore, may compile an error detection procedure, judges whether has many registers in the identical time is “1”, if has, then changes over to the corresponding disposal procedure.
4.state machine's description method
VHDL has the different description way to the different state machine, the description way causes the gate level net table which synthesizes to be also different differently, must therefore and may synthesize the sexual selection corresponding state machine description way according to digital circuit's characteristic.
① Writes about in 1 advancement module the entire state machine, in this module both description condition shift and description condition input output, namely so-called single advancement state machine. It the combinatory logic and the sequential logic will describe in an advancement, after this way's only merit will be may obtain the lock will save the output signal. But when description current condition must consider that the next condition the output, the entire code is not clear, is not easy to understand, the maintenance, also does not favor the succession restraint, the function change, the debugging and so on, moreover cannot very good expression Mealy state machine's output, easy cause the logical function to be wrong. Moreover, this kind of description is opposite in other two kind of descriptions is quite long.
② Uses 2 advancement modules, a module uses the synchronized succession description condition shift; Another module with combinatory logic judgment condition jump condition, description condition shift rule and logical output, this is the synthesizer understands the best one description way, is also under the request not high condition the most commonly used one kind.
③ Uses 3 advancement modules, a module uses the synchronized succession description condition shift; Second uses the combinatory logic judgment condition jump condition, the description condition shift rule; The third module use synchronization sequence circuit describes each condition output. Compares with the preceding description way, although code structure complex some, but trades the superiority achieved the synchronized register to output, eliminates the combinatory logic output not to stabilize with the burr hidden danger, moreover favored the succession way grouping, was better on the FPGA synthesis and the layout wiring effect.
Generally speaking, the recommendation state machine description way is the latter two kinds. Its reason: The design should better use the synchronized succession way, enhances the design the stability, eliminates the burr. After the state machine realizes, the condition shift part is the synchronization sequence circuit, but the condition jump condition's judgment is the combinatory logic. Although the second description method has many advantage, but an obvious weakness is its output use combinatory logic describes, easy to produce the burr and so on stabilizing factor, and the excessively many combinatory logic will affect the speed which in the logical component will realize, but the third kind of description way according to next condition's judgment, will check state machine's output ingeniously with the synchronization sequential logic.
5.burr and competition processing
Burr production, because on the one hand in the state machine contains has the combinatory logic advancement, causes the output signal to produce the burr in clock's effective border; On the other hand works as the status signal is many value times, as a result of transmission delay's existence, on various holding wires' value will have the change time to have the priority, will cause the condition migration time will have the temporary condition. When state machine's output signal takes other functional module the control signal use, will cause to be controlled the module to have the misoperation, will create the system work confusion. Therefore, in this case must eliminate the burr through the change design.
Eliminates the state machine output signal “the burr” to be possible generally from the following several improvements:
① When circuit design, selects the delay time small component, and uses the progression few circuit structure as far as possible; Or the clock signal introduction combination advancement, comes with the clock in-step condition migration, had guaranteed the output signal does not have the burr, but increased the output register or like this, the hardware expenses increase, this regarding some register resources few goal chip is disadvantageous; Moreover also the limit system clock's highest operating frequency; Because the clock signal will output loads to the additional register, therefore obtains the signal value time in the out-port to compare condition a change time delay clock cycle.
② The adjustment condition code, causes during the adjacent state only then 1 signal change, avoids the burr the production.
③ Takes directly state machine's condition code the output signal, namely uses the condition code direct output state machine, caused the condition and the output signal is consistent, causes the output decoding circuit to optimize. This kind of plan, takes the chip resources to be few, the signal and the change of state synchronization, the speed is quick, is one kind of superior plan. But when design process to condition code possibly increases the state vector, has the unnecessary condition. Although in the available CASE sentence WHEN-OTHERS arranges the unnecessary condition, but sometimes with difficulty active control unnecessary condition, time movement possibly will have the situation which expected with difficulty. Therefore it is suitable for the state machine output signal few situations. This way's shortcoming weakened the design readability and the maintainability.
In the Finite state machine synthesis's competition phenomenon is refers to, because the sensitive signal's frequent change causes the state machine to change the condition many times in the identical metre, interferes with electric circuit's normal work. When the output signal feeds back takes the input signal time, will have the competition. What here must point out is time which simulates before the synthesis often cannot discover in the description the latent competition phenomenon, only then after synthesis, the competition completely will only then expose. Eliminates the competition the means is creates the competition the signal from the sensitive signal table, except that but alters to by the clock signal triggers the advancement, like this causes condition one metre only to change one time.
6.state machine's optimization
The optimized goal mainly has two: Speed and scale, but the speed condition is harsher, needs the scale to be bigger, therefore time optimization circuit structure, should the overall evaluation various aspects factor, the choice optimization plan. The circuit structure divides into the logic circuit and the sequence circuit. Logic circuit's optimization including Boolean expression optimization and so on, sequence circuit including usual sequence circuit and state machine. The state machine optimizes including the choice appropriate condition and the code and so on, for instance the reasonable combination as well as reduced condition's quantity and so on can the big simplified circuit, when the programming should logic which may combine put in as far as possible in the identical syntagma, like this may optimize the circuit structure effectively.
7.conclusion
The Finite state machine is a number system's important component. This article discussed the item which and each kind of different mode of writing good and bad points in detail state machine various part and should pay attention, when the design must act according to the actual situation to make the suitable choice.
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