module check_edg(clk_slow,clk_fast,rst,dout);
input clk_slow;
input clk_fast;
input rst;
output[2:0]；
reg temp_1d;
reg temp_2d;
reg temp_3d;
always @(posedge clk_slow)
if(rst) begin
temp_1d <= 1‘b0;
end
else begin
temp_1d <= ~temp_1d;
end
always @(posedge clk_fast)
if(rst) begin
temp_2d <= 1‘b0;
temp_3d <= 1‘b0;
end
else begin
temp_2d <= temp_1d;
temp_3d <=temp_2d;
end
assign dout[0] = temp_2d && (~temp_3d); //上升沿
assign dout[1] = (~temp_2d) && temp_3d;//下降沿
assign dout[2] = (temp_2d) ^ temp_3d;//上升沿和下降沿
endmodule |
