本帖最后由 dsoyy 于 2010-4-7 17:13 编辑
我用的是飞凌的开发板OK2440-III,SD卡底层有如下API函数:
void Rd_Block(void)
{
U32 mode;
int status;
rd_cnt=0;
Uart_Printf("Block read test[ Polling read ]\n");
mode = 0 ;
// rSDICON = rSDICON|(1<<1); // FIFO reset
rSDIFSTA=rSDIFSTA|(1<<16); // FIFO reset
if(mode!=2)
rSDIDCON=(2<<22)|(1<<19)|(1<<17)|(Wide<<16)|(1<<14)|(2<<12)|(block<<0); //YH 040220
//Word Rx, Rx after cmd, blk, 4bit bus, Rx start, blk num, data start, data transmit mode
rSDICARG=0x0; // CMD17/18(addr)
RERDCMD:
switch(mode)
{
case POL:
if(block<2) // SINGLE_READ
{
rSDICCON=(0x1<<9)|(0x1<<8)|0x51; // sht_resp, wait_resp, dat, start, CMD17
if(!Chk_CMDend(17, 1)) //-- Check end of CMD17
goto RERDCMD;
}
else // MULTI_READ
{
rSDICCON=(0x1<<9)|(0x1<<8)|0x52; // sht_resp, wait_resp, dat, start, CMD18
if(!Chk_CMDend(18, 1)) //-- Check end of CMD18
goto RERDCMD;
}
rSDICSTA=0xa00; // Clear cmd_end(with rsp)
while(rd_cnt<128*block) // 512*block bytes
{
if((rSDIDSTA&0x20)==0x20) // Check timeout
{
rSDIDSTA=(0x1<<0x5); // Clear timeout flag
break;
}
status=rSDIFSTA;
if((status&0x1000)==0x1000) // Is Rx data?
{
*Rx_buffer++=rSDIDAT;
rd_cnt++;
}
}
break;
case INT:
pISR_SDI=(unsigned)Rd_Int;
rINTMSK = ~(BIT_SDI);
rSDIIMSK=5; // Last & Rx FIFO half int.
if(block<2) // SINGLE_READ
{
rSDICCON=(0x1<<9)|(0x1<<8)|0x51; // sht_resp, wait_resp, dat, start, CMD17
if(!Chk_CMDend(17, 1)) //-- Check end of CMD17
goto RERDCMD;
}
else // MULTI_READ
{
rSDICCON=(0x1<<9)|(0x1<<8)|0x52; // sht_resp, wait_resp, dat, start, CMD18
if(!Chk_CMDend(18, 1)) //-- Check end of CMD18
goto RERDCMD;
}
rSDICSTA=0xa00; // Clear cmd_end(with rsp)
while(rd_cnt<128*block);
rINTMSK |= (BIT_SDI);
rSDIIMSK=0; // All mask
break;
case DMA:
pISR_DMA0=(unsigned)DMA_end;
rINTMSK = ~(BIT_DMA0);
rSDIDCON=rSDIDCON|(1<<24); //YH 040227, Burst4 Enable
rDISRC0=(int)(SDIDAT); // SDIDAT
rDISRCC0=(1<<1)+(1<<0); // APB, fix
rDIDST0=(U32)(Rx_buffer); // Rx_buffer
rDIDSTC0=(0<<1)+(0<<0); // AHB, inc
rDCON0=(1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(2<<24)+(1<<23)+(1<<22)+(2<<20)+128*block;
//handshake, sync PCLK, TC int, single tx, single service, SDI, H/W request,
//auto-reload off, word, 128blk*num
rDMASKTRIG0=(0<<2)+(1<<1)+0; //no-stop, DMA2 channel on, no-sw trigger
// rSDIDCON=(2<<22)|(1<<19)|(1<<17)|(Wide<<16)|(1<<15)|(2<<12)|(block<<0);
rSDIDCON=(2<<22)|(1<<19)|(1<<17)|(Wide<<16)|(1<<15)|(1<<14)|(2<<12)|(block<<0);
// Word Rx, Rx after rsp, blk, 4bit bus, dma enable, Rx start, blk num, Data start, data receive mode, YH 040220
if(block<2) // SINGLE_READ
{
rSDICCON=(0x1<<9)|(0x1<<8)|0x51; // sht_resp, wait_resp, dat, start, CMD17
if(!Chk_CMDend(17, 1)) //-- Check end of CMD17
goto RERDCMD;
}
else // MULTI_READ
{
rSDICCON=(0x1<<9)|(0x1<<8)|0x52; // sht_resp, wait_resp, dat, start, CMD18
if(!Chk_CMDend(18, 1)) //-- Check end of CMD18
goto RERDCMD;
}
rSDICSTA=0xa00; // Clear cmd_end(with rsp)
while(!TR_end);
//Uart_Printf("rSDIFSTA=0x%x\n",rSDIFSTA);
rINTMSK |= (BIT_DMA0);
TR_end=0;
rDMASKTRIG0=(1<<2); //DMA0 stop
break;
default:
break;
}
//-- Check end of DATA
if(!Chk_DATend())
Uart_Printf("dat error\n");
rSDIDCON=rSDIDCON&~(7<<12); //YH 040220, Clear Data Transfer mode => no operation, Cleata Data Transfer start
rSDIFSTA=rSDIFSTA&0x200; //Clear Rx FIFO Last data Ready, YH 040221
rSDIDSTA=0x10; // Clear data Tx/Rx end detect
if(block>1)
{
RERCMD12:
//--Stop cmd(CMD12)
rSDICARG=0x0; //CMD12(stuff bit)
rSDICCON=(0x1<<9)|(0x1<<8)|0x4c;//sht_resp, wait_resp, start, CMD12
//-- Check end of CMD12
if(!Chk_CMDend(12, 1))
goto RERCMD12;
rSDICSTA=0xa00; // Clear cmd_end(with rsp)
}
} |